SystemVerilog OOP Mastery · All levels
Singleton and config_db Patterns without Global Chaos: Code Examples
Code Examples for Singleton and config_db Patterns without Global Chaos.
Code examples
Singleton configuration object with static accessor
systemverilog
class run_cfg extends uvm_object;\n `uvm_object_utils(run_cfg)\n static run_cfg m_inst;\n int unsigned timeout_cycles = 1000;\n bit enable_coverage = 1'b1;\n\n static function run_cfg get();\n if (m_inst == null)\n m_inst = run_cfg::type_id::create("run_cfg");\n return m_inst;\n endfunction\nendclassThis keeps one canonical configuration identity for the run, created lazily and factory-visible.
Publish singleton handle through config_db
systemverilog
class my_test extends uvm_test;\n `uvm_component_utils(my_test)\n function void build_phase(uvm_phase phase);\n run_cfg cfg;\n super.build_phase(phase);\n cfg = run_cfg::get();\n cfg.timeout_cycles = 2500;\n cfg.enable_coverage = 1'b0;\n uvm_config_db#(run_cfg)::set(this, "env.*", "run_cfg", cfg);\n endfunction\nendclassTests remain the policy owner while env/components consume config through explicit hierarchical wiring.
Consume config_db dependency in env and fail fast
systemverilog
class my_env extends uvm_env;\n `uvm_component_utils(my_env)\n run_cfg cfg;\n\n function void build_phase(uvm_phase phase);\n super.build_phase(phase);\n if (!uvm_config_db#(run_cfg)::get(this, "", "run_cfg", cfg))\n `uvm_fatal("CFG", "run_cfg missing from config_db")\n `uvm_info("CFG", $sformatf("timeout=%0d", cfg.timeout_cycles), UVM_LOW)\n endfunction\nendclassComponents fail clearly when wiring is absent, avoiding hidden fallback to global state that masks setup errors.