SystemVerilog OOP Mastery · All levels
Handles, new(), and Construction Patterns
SystemVerilog class assignment copies handles, not object contents, so aliasing is the default behavior. Robust construction patterns use explicit new(), null checks, and clone/copy methods to avoid accidental shared state.
Overview
SystemVerilog class assignment copies handles, not object contents, so aliasing is the default behavior. Robust construction patterns use explicit new(), null checks, and clone/copy methods to avoid accidental shared state.
Class variables are references. When you do p2 = p1, both handles target the same heap object, and any mutation through one handle is visible through the other. This is efficient for passing transactions around, but dangerous when components expect private snapshots.
In this topic
1. Concept Explained
2. Code Examples
3. SystemVerilog vs C++/Java
4. Pitfalls
5. Exercises
6. Interview QuestionsRead the concept first, study the code examples, compare against C++/Java, then test yourself with the exercises and interview questions.
Class vs handle vs object memory model
CLASS VS HANDLE VS OBJECT IN MEMORY
compile-time blueprint runtime state
+---------------------------+ +-------------------------+
| class packet; | | stack frame |
| rand bit [7:0] addr; | | packet p ------------+----+
| function void display() | | | |
| endclass | +-------------------------+ |
+---------------------------+ |
v
+-------------------------+
| heap object @0x1004 |
| addr = 8'h3C |
| display() body executes |
+-------------------------+
Class defines behavior. Handle stores a reference. Object lives on heap.