SystemVerilog OOP Mastery · All levels
Parameterized Classes with Type and Value Parameters
Use class #(type T, int N) to build one reusable class shape that stays type-safe across many transaction and storage variants.
Overview
Use class #(type T, int N) to build one reusable class shape that stays type-safe across many transaction and storage variants.
In SystemVerilog, class parameters can be both type and value parameters, so a single class declaration can adapt payload type and structural constants together. A common verification pattern is class #(type T = my_txn, int N = 16), where T controls the API type and N controls depth, width, or limits.
In this topic
diagram
1. Concept Explained
2. Code Examples
3. SystemVerilog vs C++/Java
4. Pitfalls
5. Exercises
6. Interview QuestionsRead the concept first, study the code examples, compare against C++/Java, then test yourself with the exercises and interview questions.
Class vs handle vs object memory model
diagram
CLASS VS HANDLE VS OBJECT IN MEMORY
compile-time blueprint runtime state
+---------------------------+ +-------------------------+
| class packet; | | stack frame |
| rand bit [7:0] addr; | | packet p ------------+----+
| function void display() | | | |
| endclass | +-------------------------+ |
+---------------------------+ |
v
+-------------------------+
| heap object @0x1004 |
| addr = 8'h3C |
| display() body executes |
+-------------------------+
Class defines behavior. Handle stores a reference. Object lives on heap.