SystemVerilog OOP Mastery · All levels
Parameterized Classes with Type and Value Parameters: Concept Explained
Concept Explained for Parameterized Classes with Type and Value Parameters.
Concept
In short: Use class #(type T, int N) to build one reusable class shape that stays type-safe across many transaction and storage variants.
In SystemVerilog, class parameters can be both type and value parameters, so a single class declaration can adapt payload type and structural constants together. A common verification pattern is class #(type T = my_txn, int N = 16), where T controls the API type and N controls depth, width, or limits.
Specialization is resolved when the simulator elaborates the testbench code, but object instances are still runtime handles created with new. That means you get compile/elaboration type checking per specialization while preserving standard OOP behavior such as inheritance, polymorphic handles, and dynamic construction.