SystemVerilog OOP Mastery · All levels
Specializations, typedef Aliases, and the Per-Specialization Static Gotcha
Each unique parameter combination creates a distinct class specialization, and each specialization owns its own static storage.
Overview
Each unique parameter combination creates a distinct class specialization, and each specialization owns its own static storage.
The most common bug in this topic is assuming one global static variable across all specializations. In reality, packet#(bit[7:0],16)::created and packet#(int,4)::created are independent storage locations because they belong to different specialized classes.
In this topic
diagram
1. Concept Explained
2. Code Examples
3. SystemVerilog vs C++/Java
4. Pitfalls
5. Exercises
6. Interview QuestionsRead the concept first, study the code examples, compare against C++/Java, then test yourself with the exercises and interview questions.
Class vs handle vs object memory model
diagram
CLASS VS HANDLE VS OBJECT IN MEMORY
compile-time blueprint runtime state
+---------------------------+ +-------------------------+
| class packet; | | stack frame |
| rand bit [7:0] addr; | | packet p ------------+----+
| function void display() | | | |
| endclass | +-------------------------+ |
+---------------------------+ |
v
+-------------------------+
| heap object @0x1004 |
| addr = 8'h3C |
| display() body executes |
+-------------------------+
Class defines behavior. Handle stores a reference. Object lives on heap.