SystemVerilog OOP Mastery · All levels
Static Members and Static Methods in Class-Based Testbenches
Static class state is shared by all objects of one specialization and is useful for counters, registries, and coordinated reset hooks.
Overview
Static class state is shared by all objects of one specialization and is useful for counters, registries, and coordinated reset hooks.
A static property belongs to the class specialization, not an object instance. Every object of that specialization sees the same static variable, which is ideal for IDs, coverage buckets, object pools, and singleton-like utilities.
In this topic
diagram
1. Concept Explained
2. Code Examples
3. SystemVerilog vs C++/Java
4. Pitfalls
5. Exercises
6. Interview QuestionsRead the concept first, study the code examples, compare against C++/Java, then test yourself with the exercises and interview questions.
Class vs handle vs object memory model
diagram
CLASS VS HANDLE VS OBJECT IN MEMORY
compile-time blueprint runtime state
+---------------------------+ +-------------------------+
| class packet; | | stack frame |
| rand bit [7:0] addr; | | packet p ------------+----+
| function void display() | | | |
| endclass | +-------------------------+ |
+---------------------------+ |
v
+-------------------------+
| heap object @0x1004 |
| addr = 8'h3C |
| display() body executes |
+-------------------------+
Class defines behavior. Handle stores a reference. Object lives on heap.