SystemVerilog OOP Mastery · All levels
No Multiple Inheritance (Only Interface-Class Contracts): Interview Questions
Interview Questions for No Multiple Inheritance (Only Interface-Class Contracts).
Interview questions
Q1. Why does SystemVerilog allow many interface classes but only one base class?
Answer: It separates contract polymorphism from implementation inheritance. Multiple contracts are safe; multiple implementation bases would add ambiguity the language avoids.
Q2. What is the cleanest substitute for multiple inheritance in UVM components?
Answer: Single inheritance for phase behavior plus capability interfaces and composed helpers for orthogonal features.
Q3. When does composition become worse than inheritance?
Answer: When helper boundaries are unclear and many helpers mutate shared internal state, making behavior implicit and hard to debug.