Full Topic Map

OOP Foundations in SystemVerilog
   - Classes and Objects
   - Handles, new(), and Construction Patterns
   - Encapsulation with local and protected
   - this, Scope Resolution, and Automatic Lifetime

Inheritance & Polymorphism
   - Class Inheritance with `extends`
   - Virtual Methods and Override Intent
   - Polymorphism and Dispatch Semantics
   - `super`, `super.new`, and Overriding Rules

Abstract & Interface Classes
   - Abstract Classes with `virtual class`
   - Pure Virtual Methods as Compile-Time Contracts
   - Interface Classes and `implements`
   - No Multiple Inheritance: Interface Classes + Composition

Parameterized Classes & Static Members
   - Parameterized Classes with Type and Value Parameters
   - Static Members and Static Methods in Class-Based Testbenches
   - Specializations, typedef Aliases, and the Per-Specialization Static Gotcha
   - Type-Parameter Patterns for Reusable OOP Testbench Design

Copy, Cast & Randomization
   - Shallow vs Deep Copy
   - clone() and copy() Methods
   - Dynamic Cast with $cast
   - Randomization with Constraints

What SystemVerilog OOP Lacks
   - No Multiple Inheritance (Only Interface-Class Contracts)
   - No Operator Overloading
   - No Destructors or GC APIs (Handle Lifetime Semantics)
   - Missing Features vs C++/Java and Reliable Workarounds

OOP Patterns & UVM Application
   - Factory Pattern: Polymorphism with Type and Instance Overrides
   - Callbacks and Policy Classes for Open Extension
   - Parameterized Components and Agents at Scale
   - Singleton and config_db Patterns without Global Chaos

Tricky Pitfalls & Debug
   - Object Lifetime and Null Handles
   - Handle Aliasing Bugs
   - Virtual vs Nonvirtual Traps
   - Static and Parameterized Gotchas