SystemVerilog OOP Mastery · All levels
Handle Aliasing Bugs: Interview Questions
Interview Questions for Handle Aliasing Bugs.
Interview questions
Q1. How can two distinct transaction handles still produce coupled behavior?
Answer: They can own the same nested handle member due to shallow copy, so mutating nested state via one handle affects the other.
Q2. What logging proves aliasing quickly in SV?
Answer: Print %p for both top-level and nested handles at enqueue and compare time, plus key field values before/after mutation.
Q3. When is shallow copy acceptable?
Answer: Only when shared mutable state is explicitly intended and documented; for scoreboarding and prediction flows, deep copy is usually required.