SystemVerilog OOP Mastery · All levels
Static and Parameterized Gotchas
Statics and parameterized classes interact in surprising ways: base-class statics can be globally shared, and shallow clones can alias nested handles across seemingly independent wrappers.
Overview
Statics and parameterized classes interact in surprising ways: base-class statics can be globally shared, and shallow clones can alias nested handles across seemingly independent wrappers.
A team expected pkt#(int) and pkt#(byte) counters to restart independently. IDs interleaved in logs, causing flaky ordering assertions. Root cause was static next_id declared in a non-parameterized base class, making it shared for every specialization.\n\nA second issue appeared in the same flow: wrappers were cloned shallowly, so payload handles were shared across predictor and scoreboard. Engineers thought specialization separated state, but aliasing ignored type boundaries because both wrappers referenced the same underlying object.
In this topic
1. Concept Explained
2. Code Examples
3. SystemVerilog vs C++/Java
4. Pitfalls
5. Exercises
6. Interview QuestionsRead the concept first, study the code examples, compare against C++/Java, then test yourself with the exercises and interview questions.
OOP bug root-cause decision tree
ROOT CAUSE TREE FOR OOP FAILURES
symptom: test behavior mismatch
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reproducible?
/ \
no yes
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check race/time inspect object state
/ | \
null handle aliasing wrong override
| | |
construct path clone policy virtual+factory map
\ | /
+------ implement fix ------+
Localize the failing object lifecycle before broad refactoring.