SystemVerilog OOP Mastery · All levels
Virtual vs Nonvirtual Traps: Exercises
Exercises for Virtual vs Nonvirtual Traps.
Practice exercises
Exercise 1
A UVM component stores sequencers in an array of base type and calls mode_name(). Derived classes implement mode_name(), yet logs always show base mode. What is the minimum code change?
Solution
diagram
Declare mode_name() as virtual in the base class. Then calls through base handles dispatch to derived implementations.Exercise 2
You already made run_phase() virtual, but protocol-specific formatting still looks base-only. Where is the likely design mistake?
Solution
diagram
A helper called from run_phase() is probably nonvirtual in the base class. Mark that helper virtual if it is intended as an extension point.