This capstone verifies a parameterized synchronous FIFO end to end. Planning, stimulus, checking, assertions, coverage and closure each appear once, in one environment.
CAPSTONE ENVIRONMENT MAP
┌───────────── tb_top ─────────────┐
│ clk/rst gen fifo_if │
│ ┌───────┐ │
gen ──mailbox──► drv ════════════════►│ DUT │ │
│ │ (cb drive) │ fifo │ │
scenario │ └───┬───┘ │
knobs │ ▲ bind: fifo_sva │ │
│ └────────────────┘ │
│ in_mon (push side) out_mon (pop side)
│ │ │ │
│ ▼ ▼ │
│ ┌──────── scoreboard ───────┐ │
│ │ queue model · in-order cmp│ │
│ └───────────┬───────────────┘ │
│ coverage (cov) │
└─────────────────────────────────┘
stimulus stack: gen → mailbox → drv → fifo_if
checking stack: monitors → scoreboard ← reference model
always-on: bound assertions + sampled coverageLesson | What it builds |
|---|---|
The spec, the question log, features F-01 to F-11 and the plan table. | |
Interface, harness, transactions, generator, driver and environment. | |
Passive monitors and a queue-based scoreboard. | |
Bound assertions, covergroups, regression tiers and sign-off. |
It is small enough to verify completely and rich enough to need every technique. Boundaries, simultaneity, reset, backpressure and parameter corners all fit in one design.