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Course contents

  • Start Here6
  • SystemVerilog Language Foundations35
  • Object-Oriented SystemVerilog for Verification35
  • Constraint Randomization — Interview-Critical Deep Dive66
  • SystemVerilog Assertions — Interview-Critical Deep Dive63
  • Functional Coverage in SystemVerilog28
  • Testbench Architecture in SystemVerilog38
  • Advanced Language & Integration30
  • Senior & Interview Preparation34
    • Senior Debug Playbook
      • Failure Triage Method
      • Waveform Debug Strategy
      • Debugging the Testbench
      • Hunting X's and Races
      • Three Debug Case Studies
    • Reviewing Verification Code
    • Verification Strategy: Spec to Sign-Off
    • SystemVerilog Interview Q&A Bank
    • Capstone: Verify a Parameterized FIFO
  • Principal-Level Verification28
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‹Senior & Interview Preparation
  1. Topics
  2. SystemVerilog
  3. Senior & Interview Preparation
  4. Senior Debug Playbook

Part 8 · Senior & Interview Prep · Intermediate

Senior Debug Playbook

Triage, waveform, testbench, and X and race methods with worked cases for senior debug.

  • 5topics
  • 5lessons

Topics in this section

  1. 1Failure Triage Method1 lesson
  2. 2Waveform Debug Strategy1 lesson
  3. 3Debugging the Testbench1 lesson
  4. 4Hunting X's and Races1 lesson
  5. 5Three Debug Case Studies1 lesson

Senior debug is a loop: triage the failure, shrink it to a minimal repro, hypothesize one cause, and run the cheapest experiment that falsifies it. Only the first error matters, the testbench is the prime suspect, and every fix leaves a regression behind.

Diagram
Legend: [TRIAGE] [WAVE] [TB] [X/RACE]

  THE DEBUG LOOP — every failure goes through this cycle

  failure report
       │
       ▼
  ┌─────────────────────┐
  │ 1. TRIAGE [TRIAGE]   │  first error only · classify signature
  │    where to look?    │  TB bug? RTL bug? spec ambiguity?
  └─────────┬───────────┘
            ▼
  ┌─────────────────────┐
  │ 2. REPRODUCE         │  same seed · same build · minimal test
  │    shrink the case   │  shorter sim · fewer agents · one txn
  └─────────┬───────────┘
            ▼
  ┌─────────────────────┐
  │ 3. HYPOTHESIZE       │  one suspect at a time
  │    cheapest test?    │  log? assertion? wave? code read?
  └─────────┬───────────┘
            ▼
  ┌─────────────────────┐
  │ 4. EXPERIMENT        │  waves [WAVE] · TB instrumentation [TB]
  │    falsify it        │  X-trace [X/RACE] · directed re-run
  └─────────┬───────────┘
            ▼
     hypothesis survives? ──no──► back to 3 with new evidence
            │ yes
            ▼
     fix + add a regression test that would have caught it

Lesson

What it covers

Failure Triage Method

First-error discipline, six signature classes, and the testbench versus RTL verdict.

Waveform Debug Strategy

Backward tracing, first-divergence markers, sampler pitfalls, and a monitor case.

Debugging the Testbench

Activity gates, loud failures, hang triage, and two testbench cases.

Hunting X's and Races

First-X back-propagation, reset audits, race protocol, and a gate-level case.

Check yourself A log holds 200 errors after one scoreboard mismatch. Which error do you debug first, and why?

The first one. Everything after it ran in a corrupted state, so later errors are usually echoes of the original fault.

Interview

Interviewers probe method, not tools: first-error discipline, a verdict backed by pin-level evidence, and one war story with a generalized lesson. This topic gives you all three.

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See also

  • Reviewing Verification Code
  • Verification Strategy: Spec to Sign-Off
  • SystemVerilog Interview Q&A Bank