Once a scoreboard mismatches or an assertion fires, the state after that timestamp is suspect. Sequences may desynchronize from the DUT, and later messages echo the original fault.
LOG WITH 200 ERRORS — what a senior reads
@ 12,450 ns UVM_ERROR SB: data mismatch exp=0xA4 act=0x00 ◄── ONLY THIS
@ 12,470 ns UVM_ERROR SB: data mismatch exp=0x31 act=0x00 (echo)
@ 12,490 ns UVM_ERROR SB: data mismatch exp=0x77 act=0x00 (echo)
...197 more... (noise)
Clue hidden in the noise: act is ALWAYS 0x00 after 12,450 ns
→ something stopped responding at ~12,450 ns. Debug THAT instant.In practice, find the first ERROR or FATAL and note its time. A later error with a clearer signature may guide the search, but the verdict must still hold at the first error time.
Thirty seconds of classification picks the first experiment. Each signature points at a different likely cause.
Signature | Likely cause | First experiment |
|---|---|---|
Data mismatch | Scoreboard logic, monitor sampling, or a real datapath fault | One field wrong, or all fields? |
Missing transaction | DUT dropped it, monitor missed it, predictor over-generated | Did it appear on the pins at all? |
Extra transaction | Double sampling, unmodeled retry, DUT replay | Compare counts at each pipeline stage. |
Timeout or hang | Objection or drain fault, mailbox stall, DUT stall | Where is time stuck, and on what is each thread blocked? |
Assertion failure | Often the assertion encodes the spec wrong | Read the assertion before opening waves. |
X on outputs | Reset or initialization gap | Back-propagate to the first X. |
The monitor. A time-shifted pattern points at a sampling-position fault, not corrupted data.
A failure that reproduces in a 3-transaction run can be re-simulated after every hypothesis tweak. The overnight run cannot.
REPRODUCE MINIMIZE ISOLATE
───────────── ───────────── ─────────────
same seed shorter sim binary-search time:
same build (kill after 1st err) which txn # breaks it?
same +args ──► fewer agents ──►
fails identically? fewer txn types binary-search space:
│ single sequence which component lies?
no → env diff, │ │
race, or stale still fails with smallest config that
build — fix 3 txns instead of fails = your debug
this FIRST 30,000? gold. vehicle from now onPin the seed, build, and arguments before anything else. A baseline that drifts between runs is unwinnable.
Every debug ends in one of three verdicts, and each needs positive evidence. Pin-level truth is the arbiter.
Verdict | Evidence required |
|---|---|
Testbench fault | Pins show correct DUT behavior but the checker disagrees, or the expected value is provably wrong against the spec. |
RTL fault | Pins violate the spec. Cite the spec section, the cycle, the signal, and legal stimulus. |
Spec ambiguity | Both sides read one sentence differently. Quote it and state both readings. |
One-line summary with the signature class.
Seed, build, and command line: exact reproduction in one paste.
First-error time and the minimized scenario.
Pin-level wave or log excerpt, with the spec section cited.
Verdict and confidence level, plus what would change your mind.
Testbench fault. Correct pins acquit the DUT, so the monitor or scoreboard is the suspect.