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// not-run: needs four-state X; Verilator 5.048 (tried first by the runner) ties undriven logic to 0 so $isunknown never fires; passes under Icarus
module tb_x_origin;
  timeunit 1ns; timeprecision 1ps;
  logic clk = 0;
  always #5 clk = ~clk;
  logic cfg_reset = 0;   // properly reset model
  logic cfg_missing;     // never driven: stands in for the unreset flop
  logic mask = 1;
  wire leak;
  assign leak = cfg_missing & mask;
  int errors = 0;
  initial begin
    #1;                                         // settle time 0
    if (!$isunknown(cfg_missing)) errors++;     // origin is X since time 0
    if (leak !== 1'bx) errors++;                // X fans out through live logic
    if (cfg_reset !== 0) errors++;
    @(posedge clk); #1;
    if (!$isunknown(cfg_missing)) errors++;     // still X after a clock
    if (errors == 0) $display("PASS: unreset flop reads X since time 0 and leaks through live logic");
    else $fatal(1, "FAIL: X-origin check");
    $finish;
  end
endmodule

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module tb_origin_trace;
  timeunit 1ns; timeprecision 1ps;
  logic clk = 0;
  always #5 clk = ~clk;
  // Two-state version of the X hunt: each value carries a validity flag.
  logic [7:0] cfg_good = 8'hA5;
  bit valid_good = 1;        // reset path validates its register
  logic [7:0] cfg_missing = 8'h00;
  bit valid_missing = 0;     // never validated: the unreset flop
  bit data_valid = 0;        // live data arrives later
  wire [7:0] gated;
  assign gated = cfg_missing & {8{cfg_good[0]}};
  // Two pipeline stages. Each flop's flag is the AND of its input flags.
  bit s1_ok = 0, s2_ok = 0;      // path fed by the validated register
  bit s1_bad = 0, s2_bad = 0;    // path fed by the unvalidated origin
  always_ff @(posedge clk) begin
    s1_ok  <= data_valid & valid_good;
    s2_ok  <= s1_ok;
    s1_bad <= data_valid & valid_missing;
    s2_bad <= s1_bad;
  end
  int errors = 0;
  initial begin
    #1;
    if (valid_missing !== 0) errors++;   // origin flagged since time 0
    @(negedge clk);
    data_valid = 1;                      // live data arrives
    @(posedge clk); #1;
    if (s1_ok !== 1 || s2_ok !== 0) errors++;   // clean flag reaches stage 1
    if (s1_bad !== 0) errors++;                 // tainted flag stays invalid
    @(posedge clk); #1;
    if (s2_ok !== 1) errors++;                  // clean flag reaches stage 2
    if (s2_bad !== 0) errors++;                 // invalidity traced to stage 2
    if (gated !== 8'h00) errors++;              // data path stays deterministic
    if (errors == 0) $display("PASS: unvalidated origin flagged since time 0 and traced through two live stages");
    else $fatal(1, "FAIL: origin-trace check");
    $finish;
  end
endmodule

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module race_dut (
  input logic clk,
  input logic d,
  output logic q
);
  logic q_r = 0;
  always_ff @(posedge clk) q_r <= d;
  assign q = q_r;
endmodule

module tb_drive_order;
  timeunit 1ns; timeprecision 1ps;
  logic clk = 0, d = 0, q;
  always #5 clk = ~clk;
  race_dut dut (.*);
  int errors = 0;
  initial begin
    @(negedge clk);
    d <= 1;                    // setup-respecting drive: settled before the edge
    @(posedge clk); #1;
    if (q !== 1) errors++;     // captured cleanly
    @(posedge clk);
    #1 d = 0;                  // blocking change after the edge: too late to sample
    if (q !== 1) errors++;     // flop still holds the sampled 1
    @(posedge clk); #1;
    if (q !== 0) errors++;     // the 0 lands on the next edge
    if (errors == 0) $display("PASS: setup drive captured at the edge, late drive waited a cycle");
    else $fatal(1, "FAIL: drive-ordering check");
    $finish;
  end
endmodule