Waveform Debug Strategy

Trace backward from the symptom

The amateur waveform session starts at time zero and scrolls right, hoping to notice something. The senior session starts at the symptom cycle — the first-error time from triage — and walks backward through the cone of logic that produced the bad value. Each step asks one question: which input to this stage was already wrong? Repeat until you reach a stage whose inputs are all correct but whose output is wrong. That stage contains the bug.

BACKWARD TRACE — symptom to origin

  symptom @ 12,450 ns: dut.rdata = 0x00 (expected 0xA4)
       │
       ▼ what drives rdata?
  mem_rd_data was 0x00 ◄── already wrong? YES → keep going back
       │
       ▼ what drives mem_rd_data?
  mem array @ addr 0x1F4 holds 0x00 ◄── wrong? YES → when was it written?
       │
       ▼ search last write to 0x1F4
  @ 9,120 ns: wr_en=1, wr_addr=0x1F4, wr_data=0xA4  ◄── write was CORRECT
       │
       ▼ so the write was lost — look between 9,120 and 12,450
  @ 9,121 ns: mem_clr pulse (!)  ◄── ORIGIN: clear fired mid-traffic
       │
       ▼ what asserted mem_clr? ... and so on, into the bug's home stage

Two practical tools make backward tracing fast: the driver/load trace feature of your wave viewer (jump from a signal to whatever drives it), and searching for value transitions rather than scrolling (jump to the previous edge of a signal instead of eyeballing thousands of cycles).

Mark the first-divergence cycle

Backward tracing converges on the single most valuable timestamp in any debug: the first-divergence cycle — the earliest cycle where the DUT's state differs from the golden expectation. Before that cycle everything is provably fine; after it, everything is contaminated. Place a named marker there. All hypotheses must explain what changed at that exact cycle, which instantly kills whole families of wrong theories ('the config was bad from the start' cannot be true if divergence begins at cycle 9,121).

Finding divergence without a golden trace

• Diff against a passing seed: load passing and failing runs side by side, align on a common event, and bisect for the first cycle where they differ.

• Diff against the reference model: add a debug print of model state per txn, and find the first txn where model and DUT disagree — then open waves only around that txn.

• Bisect with assertions: drop an immediate assertion on the suspect invariant and re-run the minimized case; its first failure time is your divergence marker.

Signal grouping and bookmark discipline

A debug session that will last more than ten minutes deserves thirty seconds of setup: build one group per interface (request pins, response pins, clocks/resets), one group for the suspect internal stage, and save the layout. Add bookmarks/markers with names — first_err, divergence, last_good_write — instead of memorizing timestamps. When you hand off the debug or resume tomorrow, the saved session is the difference between continuing and starting over.

When waves mislead

Waveforms feel like ground truth, but two classes of artifact routinely send debuggers down false trails. Knowing them is the difference between an hour and a day.

Assertion sampled values vs displayed values

Concurrent assertions sample in the Preponed region — the value a signal had just before the clock edge. The wave viewer displays the post-edge value at that timestamp. So an assertion can legitimately fail at a cycle where the waveform 'clearly' shows the signal correct, because the assertion saw the pre-edge value. Always evaluate assertion failures against the value one delta before the edge, or use the simulator's assertion-debug view which shows sampled values directly.

Delta cycles and zero-time ordering

• Multiple events at the same timestamp execute in delta-cycle order the wave viewer may flatten — two signals 'changing simultaneously' may have a real causal order invisible at default zoom.

• Expand delta time (most viewers support it) when debugging same-timestamp causality, especially around clock gating and derived clocks.

• TB signals driven with blocking assignments in the Active region can appear to change 'before' the clock that caused them — an artifact of region ordering, not time travel.

• A signal not in the dump scope shows its last dumped value or X — verify your dump scope covers the suspect hierarchy before concluding anything.

Key takeaways

• Start at the symptom and trace backward through the logic cone; never scroll forward from time zero.

• The first-divergence cycle is the debug's anchor — mark it, and require every hypothesis to explain it.

• Group signals by interface and name your markers; saved sessions make debug resumable and transferable.

• Assertions sample pre-edge (Preponed) values — the wave display can disagree with what the assertion saw.

Common pitfalls

• Scrolling from t=0 hoping to notice something — hours lost before reaching the symptom.

• Trusting the displayed value at a clock edge when judging an assertion failure — check the sampled value.

• Debugging with signals missing from the dump scope and misreading stale values as real.

• Not saving the wave session — tomorrow you re-derive everything you knew today.