A testbench draft starts from a corner list, not from stimulus code. Boundaries, resets, terminal counts, and sign flips are the usual entries.
Ask for the corner list as a table with expected values. Each row becomes one check.
Corner | Stimulus | Expected |
|---|---|---|
Zero and all-ones | 0x00 and 0xFF on each operand | Reference model agrees on both. |
Sign flip | 0x7F against 0x80 | Signed and unsigned orders compared explicitly. |
Terminal count | Counter at its maximum | Specified wrap, saturation, or hold behavior and any required pulse timing. |
Reset during activity | Reset asserted mid-sequence | Specified reset values at the specified synchronous or asynchronous observation point. |
The logic [7:0] operands here are unsigned. SystemVerilog uses the same comparison operators, such as >, for signed and unsigned comparisons; operand types and expression sizing determine the interpretation. There is no separate signed greater-than operator.
Here $signed(a) and $signed(b) reinterpret both equal-width operands as signed without changing their bits. Review mixed widths, unsigned operands, literals, and casts in the actual expression rather than assuming one cast fixes every case. The proposed loop checks all 65536 two-state operand pairs for this example.
operand pairs: 256 x 256 = 65536
pairs with differing signs: 2 x 128 x 128 = 32768
disagreement share: 32768 / 65536 = 0.5 = 50%
conclusion: without a signed compare, half the input space orders wrongAsk for expected values computed in the testbench, not eyeballed waveforms. Every stimulus gets a check on the same line of thought.
Reference values come from plain integer arithmetic in the testbench. The DUT never grades its own work.
The maximum block below is an illustrative example written for this course, never real assistant output. Its unsigned compare misorders every mixed-sign pair under the stated signed intent. The expected mismatch count is derived from the operand space, not an executed simulation.
// Illustrative example written for this course, never real model output.
module gen_max_buggy (
input logic [7:0] a, b,
output logic [7:0] mx
);
always_comb mx = (a > b) ? a : b; // BUG: unsigned compare of signed intent
endmodule
module gen_max_fixed (
input logic [7:0] a, b,
output logic [7:0] mx
);
always_comb mx = ($signed(a) > $signed(b)) ? a : b;
endmodule
The buggy unsigned version returns 8'hFF. The fixed signed version returns 8'h01, since minus 1 is less than plus 1.
FF versus 01 explains the symptom as minus 1 versus plus 1. The proposed loop checks the full two-state operand domain against the reference. Review the reference separately; the loop cannot establish requirements, X/Z behavior, or implementation timing.