Ask whether every output is assigned on every path. A missing path holds its old value, and holding needs a latch.
The usual fixes are a default assignment first or a complete case with default. Either one removes the hold.
Pattern asked for | Latch when | Fix demanded |
|---|---|---|
if without else | The condition is false | Add else or assign a default first. |
case without default | An uncovered select arrives | Add default or assign a default first. |
Output assigned on some branches | Other branches run | Assign every output on every path. |
Ask for the width of every expression and assignment. Truncation hides in concatenations, shifts, and mixed widths.
Connect each review concern to source evidence and an expected result. An unresolved reset or width question needs attention before polishing style.
Review area | Evidence | Question |
|---|---|---|
Interface and widths | Declarations, casts, assignments | Can each destination represent every required result? |
Reset and clocks | Event control and reset branch | Does reset act at the specified observation point? |
Corner behavior | Branches and defaults | What happens for select 3 after select 1? |
Style and naming | Project conventions | Are accepted events and state updates clearly named? |
Ask which requirements and environmental assumptions need checks. State each property in words, identify its sampling point and reset behavior, and name a counterexample. Assuming select 3 never occurs is different from requiring zero when it occurs.
This synthetic mux exercise explicitly requires y=0 for select 3. Zero is an exercise value, not a universal safe response. The checks below illustrate selected inputs; no assertion compilation or simulation result is claimed.
schematic exchange (not real output from any system):
ask: "the exercise requires zero for select 3. identify a failing transition
and a proposed check after combinational settling."
reply: "drive select 1 with b=B2, then select 3; expect y=00, not B2."
verdict: a planned check of the stated requirement. A clocked SVA draft
would additionally need a sampling clock and reset context.The mux below is an illustrative example written for this course, never real assistant output. Its missing select holds stale data, and the corrected version returns the exercise's specified zero.
// Illustrative example written for this course, never real model output.
module gen_mux_buggy (
input logic [1:0] sel,
input logic [7:0] a, b, c,
output logic [7:0] y
);
always @* begin // plain always @* mirrors the pasted snippet
case (sel)
2'd0: y = a;
2'd1: y = b;
2'd2: y = c;
// BUG: sel == 3 missing, no default: y holds its old value
endcase
end
endmodule
module gen_mux_fixed (
input logic [1:0] sel,
input logic [7:0] a, b, c,
output logic [7:0] y
);
always_comb begin
y = 8'h00; // default covers sel == 3
case (sel)
2'd0: y = a;
2'd1: y = b;
2'd2: y = c;
default: ;
endcase
end
endmodule
module tb_mux_default;
logic [1:0] sel;
logic [7:0] a, b, c, y_b, y_f;
int errors = 0;
gen_mux_buggy bb (.sel(sel), .a(a), .b(b), .c(c), .y(y_b));
gen_mux_fixed ff (.sel(sel), .a(a), .b(b), .c(c), .y(y_f));
initial begin
a = 8'hA1; b = 8'hB2; c = 8'hC3;
sel = 2'd1; #1;
if (y_b !== 8'hB2) errors++;
if (y_f !== 8'hB2) errors++;
sel = 2'd3; #1;
if (y_b !== 8'hB2) errors++;
if (y_f !== 8'h00) errors++;
sel = 2'd0; #1;
if (y_b !== 8'hA1) errors++;
if (y_f !== 8'hA1) errors++;
if (errors == 0) $display("PASS: buggy mux holds stale data, corrected mux returns specified zero");
$finish;
end
endmoduleIt reads 8'hB2. No branch assigns it, so it holds its old value, which synthesis builds as a latch.
It returns 8'h00. The default assignment before the case decides it, covering every select the branches miss.