SystemVerilog assertions check behavior over time. Two facts explain nearly every confusion about them: assertions sample signals just before the clock edge, and a fresh evaluation attempt starts on every clock tick.
Layer | Question it answers | Example |
|---|---|---|
Boolean | What is true right now |
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Sequence | What pattern spans cycles |
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Property | What must follow, and when |
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Directive | What does the tool do |
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Lesson | What it covers |
|---|---|
Instant checks, deferred forms, and where each belongs. | |
Booleans, sequences, properties, directives, and reuse. | |
Preponed sampling, clock sources, and reset gating. | |
Attempts every tick, threads, vacuity, and cost. | |
What each directive instructs, plus actions and labels. |
The value from just before the edge. Sampling happens in the preponed region, so an edge-aligned change becomes visible only at the next edge.
Every lesson in this topic ends with a bench that runs real assertions on Verilator 5.048, with a planted bug the assertion must catch. One tool fact shapes all of them: Verilator stops the run at the first $error or at the first failing assertion that has no action block, so the benches count failures in the action block instead (else fails++) and keep going.