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Course contents

  • Start Here6
  • SystemVerilog Language Foundations28
  • Object-Oriented SystemVerilog for Verification30
  • Constraint Randomization — Interview-Critical Deep Dive36
  • SystemVerilog Assertions — Interview-Critical Deep Dive40
    • SVA Fundamentals
    • Sequences: Temporal Building Blocks
      • Cycle Delays: ##N and ##[M:N]
      • Repetition: [*], [->], [=]
      • Composition: and, or, intersect, throughout, within
      • first_match() & Sequence Endpoints
    • Implication and Property Operators
    • Sampled Value Functions
    • Protocol Assertion Cookbook
    • Advanced SVA: Local Variables, Multiclock & More
    • Assertion Debug & Methodology
    • SVA Interview Drills
  • Functional Coverage in SystemVerilog22
  • Testbench Architecture in SystemVerilog23
  • Advanced Language & Integration25
  • Senior & Interview Preparation21
  • Principal-Level Verification28
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‹SystemVerilog Assertions — Interview-Critical Deep Dive
  1. Topics
  2. SystemVerilog
  3. SystemVerilog Assertions — Interview-Critical Deep Dive
  4. Sequences: Temporal Building Blocks

Part 4 · Assertions (SVA) · Intermediate

Sequences: Temporal Building Blocks

Sequences are patterns over clock ticks; delays, repetition, and composition build them on match threads.

  • 4topics
  • 4lessons

A sequence is a pattern of boolean expressions spread across clock cycles. A boolean expression is a one-cycle sequence, delays glue expressions across time, repetition compresses repeats, and composition combines patterns.

One model explains every operator below. A ranged delay or repetition forks a match thread per legal choice, and the sequence matches when any thread reaches its end.

Layer

Operator

Job

Boolean

req && !busy

One-cycle base case

Delay

a ##2 b, a ##[1:3] b

Glue across ticks; ranges fork threads

Repetition

a [*3], a [->3], a [=3]

Compress repeats and scattered counts

Composition

and, or, intersect

Combine patterns from a common start

Qualifiers

throughout, within, first_match

Constrain windows, prune threads

Property

antecedent |-> consequent

The assertion built on sequences

Lesson

Idea

Cycle Delays: fixed and ranged ##

Fixed, ranged, and unbounded delays with the thread model and zero-delay fusion.

Repetition: consecutive, goto, non-consecutive

Consecutive runs plus goto and non-consecutive counting on one shared stimulus.

Composition: and, or, intersect, throughout, within

Joining patterns, pinning lengths, invariants, and containment.

first_match() & Sequence Endpoints

Pruning thread explosion and reusing endpoints as events.

Every lesson below ends with a bench that runs real assertions on Verilator 5.048 with planted bugs. Verilator checks single-thread sequences correctly: fixed delays, a range at the very end, written-out repetition, throughout over a fixed window. Sequences that fork and then continue (a range or goto followed by more, repetition or and in a consequent) compiled and missed some or all planted failures, while covers on the same sequences counted correctly. The benches show the compact form's count beside a form that works, and What the Open Simulators Run lists every case.

Check yourself A ranged delay admits three delays and the signal arrives twice in the window. How many matches does one attempt produce?

Two, one per satisfied thread. A ranged operator never picks one interpretation; every thread that completes is a match.

Interview

Likely question: “What is a match thread?” Say a ranged operator forks one thread per legal choice and the sequence matches when any thread completes. Then name the three places it bites: ranged delays, goto versus non-consecutive endpoints, and first_match pruning.

PreviousNext: Cycle Delays: ##N and ##[M:N]

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Up nextCycle Delays: ##N and ##[M:N]

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See also

  • SVA Fundamentals
  • Implication and Property Operators
  • Sampled Value Functions