Sampled Value Functions · SystemVerilog

Part 4 · Assertions (SVA) · Intermediate

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Assertions never see live signals. At each clocking event the simulator takes a snapshot just before the edge, and every check below reasons about those snapshots.

Family	Functions	Question answered
Compare two snapshots	`$rose`, `$fell`, `$stable`, `$changed`	Did the signal move since the last tick.
Reach N back	`$past` with gate and clock arguments	What was this value N qualifying beats ago.
Classify one snapshot	`$countones`, `$onehot`, `$onehot0`, `$isunknown`	Is this vector well-formed right now.

Lesson	Idea
Edges between snapshots	Rose, fell, stable, and changed on sampled values, plus the LSB rule.
Past and gated history	Looking N beats back through bubbles with the gating argument.
One-snapshot classifiers	Counting ones, one-hot rules, and X-safe checks.
Assembling real checks	Delayed equality, stability, readback, and phase matching.

Check yourself $rose(bus) on an 8-bit bus fires. Which bit moved?

Only bit 0 is known to have risen. $rose watches the least significant bit alone, so a bus needs $changed or a reduction such as $rose(|bus).

Up next$rose, $fell, $stable, $changed

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