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Course contents

  • Start Here6
  • SystemVerilog Language Foundations28
  • Object-Oriented SystemVerilog for Verification30
  • Constraint Randomization — Interview-Critical Deep Dive36
  • SystemVerilog Assertions — Interview-Critical Deep Dive40
    • SVA Fundamentals
    • Sequences: Temporal Building Blocks
    • Implication and Property Operators
    • Sampled Value Functions
    • Protocol Assertion Cookbook
      • Valid/Ready Handshake
      • Req/Ack + Pulse Discipline
      • FIFO Rulesets
      • FSM Rulesets
      • Pipelines, Stall, Credits
    • Advanced SVA: Local Variables, Multiclock & More
    • Assertion Debug & Methodology
    • SVA Interview Drills
  • Functional Coverage in SystemVerilog22
  • Testbench Architecture in SystemVerilog23
  • Advanced Language & Integration25
  • Senior & Interview Preparation21
  • Principal-Level Verification28
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‹SystemVerilog Assertions — Interview-Critical Deep Dive
  1. Topics
  2. SystemVerilog
  3. SystemVerilog Assertions — Interview-Critical Deep Dive
  4. Protocol Assertion Cookbook

Part 4 · Assertions (SVA) · Intermediate

Protocol Assertion Cookbook

Complete SVA rulesets for handshakes, FIFOs, FSMs and pipelines, with checkers and testbenches.

  • 5topics
  • 5lessons

Each interface in this topic gets a complete ruleset. A ruleset pairs safety rules with bounded liveness, X-safety and cover points.

Family

Safety core

Liveness and cover

Handshake (valid/ready, req/ack)

Offers held until accepted; payload stable

Bounded accept window; back-to-back and stall covers

Storage (FIFO)

No overflow or underflow; count matches pointers

Full-to-empty drain cover; pointer-wrap cover

Control (FSM, pulses, interrupts)

Legal arcs only; one-hot encoding; mutex

Bounded exit from busy states; arc covers

Datapath (pipelines, credits)

Gated-latency equality; stall freezes stages

In-order retirement; credit bound and conservation

Lesson

Ruleset

Valid/Ready Handshake

Stability, X-safety, bounded acceptance and covers.

Req/Ack + Pulse Discipline

Hold, ack window, one pulse per request, spacing.

FIFO Rulesets

Legality, count and pointer math, data integrity.

FSM Rulesets

Encoding, legal arcs, bounded exit, reset, covers.

Pipelines, Stall, Credits

Gated latency, stall hold, ordering, credit bound.

Check yourself A checker has five assertions and zero cover points. What is missing?

Proof that the checker ever ran. Covers record back-to-back transfers, stalls, drains and rare arcs across the regression. A ruleset with no hits proves nothing about the design.

Interview

Whiteboard prompts for this topic grade completeness. “Write the assertions for a valid/ready channel” or “what would you check on a FIFO” expect the full ruleset unprompted, with one waveform that shows the key trace.

PreviousNext: Valid/Ready Handshake

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See also

  • SVA Fundamentals
  • Sequences: Temporal Building Blocks
  • Implication and Property Operators