Step-by-step analysis walkthrough

Use when you own MAC Arrays & Systolic in an AI-VLSI review room.

1. Capture failing metric window and workload context.

2. Map decision path: data -> model -> runtime -> hardware.

3. Check data leakage, split hygiene, and feature drift.

4. Inspect model outputs and calibration behavior.

5. Profile compute, memory traffic, and scheduling overhead.

6. Classify root cause and choose owner.

7. Patch minimally and stage rollout gates.

8. Run full regression and update signoff memo.

Artifacts to collect

• array mapping sheet, utilization report, and cycle-accurate trace

• dataset/model version tags

• runtime profile

• deployment KPI dashboard

• rollback plan

Decision memo template

AI-VLSI DECISION MEMO — MAC Arrays & Systolic
metric:
root cause:
fix:
validation:
owners: accelerator architect, microarchitecture owner, verification owner

Reference visuals

Systolic data movement

SYSTOLIC ARRAY

inputs stream horizontally
weights stream vertically
partial sums accumulate in PEs

Utilization depends on tile shape + scheduling.

AI-VLSI deep dive

Dataflow and memory hierarchy choices dominate practical accelerator performance.

Concept diagram

ACCELERATOR STACK

MAC array -> dataflow map -> SRAM hierarchy -> NoC/DRAM

Metric graph

BOTTLENECK MIX

array underutilization ████
SRAM pressure          ███████
NoC/DRAM congestion    ██████

Reports and artifacts

• array utilization

• reuse factor report

• buffer hit analysis

• NoC/DRAM bottleneck trace

Mini case study

A dataflow change improved reuse but exposed NoC congestion, requiring route-policy updates.

Debug branches

• Map reuse factors

• Inspect memory stall sources

• Profile NoC arbitration

Senior review question

Ask: what evidence connects this ML claim to a concrete VLSI workflow decision and owner signoff?

Key takeaways

• Every AI claim should map to a measurable engineering outcome.

• Validate both model quality and hardware/runtime feasibility before adoption.

Common pitfalls

• Optimizing benchmark metrics that do not correlate with signoff goals.

• Ignoring data drift and calibration after deployment.

• Shipping ML workflows without clear rollback ownership.

Execution drill pack 1

Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/step-by-step-walkthrough: metric framing, mechanism proof, hardware implications, and release safety.

Evidence checklist

• Metric context includes workload, dataset slice, and revision tags.

• Mechanism explanation links model behavior to observed outcome.

• Hardware/runtime feasibility is profiled, not assumed.

• Owner and rollback path are documented before rollout.

Review prompts

1. Which decision will this model output influence?

2. What is the first failing layer when metric regresses?

3. Which owner applies the smallest reversible fix?

4. What validation matrix is required before deployment?

Evidence capsule

AI-VLSI EVIDENCE CAPSULE 1

PATH: ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/step-by-step-walkthrough
WORKLOAD SLICE: <name>
PRIMARY METRIC: <value/trend>
FIRST FAILING LAYER: <data/model/runtime/hardware>
OWNER: <name>
PRIMARY ARTIFACT: <report/profile/dashboard>
DECISION: <ship / rollback / escalate>

Execution drill pack 2

Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/step-by-step-walkthrough: metric framing, mechanism proof, hardware implications, and release safety.

Evidence checklist

• Metric context includes workload, dataset slice, and revision tags.

• Mechanism explanation links model behavior to observed outcome.

• Hardware/runtime feasibility is profiled, not assumed.

• Owner and rollback path are documented before rollout.

Review prompts

1. Which decision will this model output influence?

2. What is the first failing layer when metric regresses?

3. Which owner applies the smallest reversible fix?

4. What validation matrix is required before deployment?

Evidence capsule

AI-VLSI EVIDENCE CAPSULE 2

PATH: ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/step-by-step-walkthrough
WORKLOAD SLICE: <name>
PRIMARY METRIC: <value/trend>
FIRST FAILING LAYER: <data/model/runtime/hardware>
OWNER: <name>
PRIMARY ARTIFACT: <report/profile/dashboard>
DECISION: <ship / rollback / escalate>

Execution drill pack 3

Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/step-by-step-walkthrough: metric framing, mechanism proof, hardware implications, and release safety.

Evidence checklist

• Metric context includes workload, dataset slice, and revision tags.

• Mechanism explanation links model behavior to observed outcome.

• Hardware/runtime feasibility is profiled, not assumed.

• Owner and rollback path are documented before rollout.

Review prompts

1. Which decision will this model output influence?

2. What is the first failing layer when metric regresses?

3. Which owner applies the smallest reversible fix?

4. What validation matrix is required before deployment?

Evidence capsule

AI-VLSI EVIDENCE CAPSULE 3

PATH: ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/step-by-step-walkthrough
WORKLOAD SLICE: <name>
PRIMARY METRIC: <value/trend>
FIRST FAILING LAYER: <data/model/runtime/hardware>
OWNER: <name>
PRIMARY ARTIFACT: <report/profile/dashboard>
DECISION: <ship / rollback / escalate>

Execution drill pack 4

Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/step-by-step-walkthrough: metric framing, mechanism proof, hardware implications, and release safety.

Evidence checklist

• Metric context includes workload, dataset slice, and revision tags.

• Mechanism explanation links model behavior to observed outcome.

• Hardware/runtime feasibility is profiled, not assumed.

• Owner and rollback path are documented before rollout.

Review prompts

1. Which decision will this model output influence?

2. What is the first failing layer when metric regresses?

3. Which owner applies the smallest reversible fix?

4. What validation matrix is required before deployment?

Evidence capsule

AI-VLSI EVIDENCE CAPSULE 4

PATH: ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/step-by-step-walkthrough
WORKLOAD SLICE: <name>
PRIMARY METRIC: <value/trend>
FIRST FAILING LAYER: <data/model/runtime/hardware>
OWNER: <name>
PRIMARY ARTIFACT: <report/profile/dashboard>
DECISION: <ship / rollback / escalate>

Execution drill pack 5

Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/step-by-step-walkthrough: metric framing, mechanism proof, hardware implications, and release safety.

Evidence checklist

• Metric context includes workload, dataset slice, and revision tags.

• Mechanism explanation links model behavior to observed outcome.

• Hardware/runtime feasibility is profiled, not assumed.

• Owner and rollback path are documented before rollout.

Review prompts

1. Which decision will this model output influence?

2. What is the first failing layer when metric regresses?

3. Which owner applies the smallest reversible fix?

4. What validation matrix is required before deployment?

Evidence capsule

AI-VLSI EVIDENCE CAPSULE 5

PATH: ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/step-by-step-walkthrough
WORKLOAD SLICE: <name>
PRIMARY METRIC: <value/trend>
FIRST FAILING LAYER: <data/model/runtime/hardware>
OWNER: <name>
PRIMARY ARTIFACT: <report/profile/dashboard>
DECISION: <ship / rollback / escalate>

Execution drill pack 6

Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/step-by-step-walkthrough: metric framing, mechanism proof, hardware implications, and release safety.

Evidence checklist

• Metric context includes workload, dataset slice, and revision tags.

• Mechanism explanation links model behavior to observed outcome.

• Hardware/runtime feasibility is profiled, not assumed.

• Owner and rollback path are documented before rollout.

Review prompts

1. Which decision will this model output influence?

2. What is the first failing layer when metric regresses?

3. Which owner applies the smallest reversible fix?

4. What validation matrix is required before deployment?

Evidence capsule

AI-VLSI EVIDENCE CAPSULE 6

PATH: ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/step-by-step-walkthrough
WORKLOAD SLICE: <name>
PRIMARY METRIC: <value/trend>
FIRST FAILING LAYER: <data/model/runtime/hardware>
OWNER: <name>
PRIMARY ARTIFACT: <report/profile/dashboard>
DECISION: <ship / rollback / escalate>

Execution drill pack 7

Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/step-by-step-walkthrough: metric framing, mechanism proof, hardware implications, and release safety.

Evidence checklist

• Metric context includes workload, dataset slice, and revision tags.

• Mechanism explanation links model behavior to observed outcome.

• Hardware/runtime feasibility is profiled, not assumed.

• Owner and rollback path are documented before rollout.

Review prompts

1. Which decision will this model output influence?

2. What is the first failing layer when metric regresses?

3. Which owner applies the smallest reversible fix?

4. What validation matrix is required before deployment?

Evidence capsule

AI-VLSI EVIDENCE CAPSULE 7

PATH: ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/step-by-step-walkthrough
WORKLOAD SLICE: <name>
PRIMARY METRIC: <value/trend>
FIRST FAILING LAYER: <data/model/runtime/hardware>
OWNER: <name>
PRIMARY ARTIFACT: <report/profile/dashboard>
DECISION: <ship / rollback / escalate>

Execution drill pack 8

Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/step-by-step-walkthrough: metric framing, mechanism proof, hardware implications, and release safety.

Evidence checklist

• Metric context includes workload, dataset slice, and revision tags.

• Mechanism explanation links model behavior to observed outcome.

• Hardware/runtime feasibility is profiled, not assumed.

• Owner and rollback path are documented before rollout.

Review prompts

1. Which decision will this model output influence?

2. What is the first failing layer when metric regresses?

3. Which owner applies the smallest reversible fix?

4. What validation matrix is required before deployment?

Evidence capsule

AI-VLSI EVIDENCE CAPSULE 8

PATH: ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/step-by-step-walkthrough
WORKLOAD SLICE: <name>
PRIMARY METRIC: <value/trend>
FIRST FAILING LAYER: <data/model/runtime/hardware>
OWNER: <name>
PRIMARY ARTIFACT: <report/profile/dashboard>
DECISION: <ship / rollback / escalate>

Execution drill pack 9

Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/step-by-step-walkthrough: metric framing, mechanism proof, hardware implications, and release safety.

Evidence checklist

• Metric context includes workload, dataset slice, and revision tags.

• Mechanism explanation links model behavior to observed outcome.

• Hardware/runtime feasibility is profiled, not assumed.

• Owner and rollback path are documented before rollout.

Review prompts

1. Which decision will this model output influence?

2. What is the first failing layer when metric regresses?

3. Which owner applies the smallest reversible fix?

4. What validation matrix is required before deployment?

Evidence capsule

AI-VLSI EVIDENCE CAPSULE 9

PATH: ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/step-by-step-walkthrough
WORKLOAD SLICE: <name>
PRIMARY METRIC: <value/trend>
FIRST FAILING LAYER: <data/model/runtime/hardware>
OWNER: <name>
PRIMARY ARTIFACT: <report/profile/dashboard>
DECISION: <ship / rollback / escalate>

Execution drill pack 10

Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/step-by-step-walkthrough: metric framing, mechanism proof, hardware implications, and release safety.

Evidence checklist

• Metric context includes workload, dataset slice, and revision tags.

• Mechanism explanation links model behavior to observed outcome.

• Hardware/runtime feasibility is profiled, not assumed.

• Owner and rollback path are documented before rollout.

Review prompts

1. Which decision will this model output influence?

2. What is the first failing layer when metric regresses?

3. Which owner applies the smallest reversible fix?

4. What validation matrix is required before deployment?

Evidence capsule

AI-VLSI EVIDENCE CAPSULE 10

PATH: ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/step-by-step-walkthrough
WORKLOAD SLICE: <name>
PRIMARY METRIC: <value/trend>
FIRST FAILING LAYER: <data/model/runtime/hardware>
OWNER: <name>
PRIMARY ARTIFACT: <report/profile/dashboard>
DECISION: <ship / rollback / escalate>

Execution drill pack 11

Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/step-by-step-walkthrough: metric framing, mechanism proof, hardware implications, and release safety.

Evidence checklist

• Metric context includes workload, dataset slice, and revision tags.

• Mechanism explanation links model behavior to observed outcome.

• Hardware/runtime feasibility is profiled, not assumed.

• Owner and rollback path are documented before rollout.

Review prompts

1. Which decision will this model output influence?

2. What is the first failing layer when metric regresses?

3. Which owner applies the smallest reversible fix?

4. What validation matrix is required before deployment?

Evidence capsule

AI-VLSI EVIDENCE CAPSULE 11

PATH: ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/step-by-step-walkthrough
WORKLOAD SLICE: <name>
PRIMARY METRIC: <value/trend>
FIRST FAILING LAYER: <data/model/runtime/hardware>
OWNER: <name>
PRIMARY ARTIFACT: <report/profile/dashboard>
DECISION: <ship / rollback / escalate>

Execution drill pack 12

Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/step-by-step-walkthrough: metric framing, mechanism proof, hardware implications, and release safety.

Evidence checklist

• Metric context includes workload, dataset slice, and revision tags.

• Mechanism explanation links model behavior to observed outcome.

• Hardware/runtime feasibility is profiled, not assumed.

• Owner and rollback path are documented before rollout.

Review prompts

1. Which decision will this model output influence?

2. What is the first failing layer when metric regresses?

3. Which owner applies the smallest reversible fix?

4. What validation matrix is required before deployment?

Evidence capsule

AI-VLSI EVIDENCE CAPSULE 12

PATH: ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/step-by-step-walkthrough
WORKLOAD SLICE: <name>
PRIMARY METRIC: <value/trend>
FIRST FAILING LAYER: <data/model/runtime/hardware>
OWNER: <name>
PRIMARY ARTIFACT: <report/profile/dashboard>
DECISION: <ship / rollback / escalate>

Execution drill pack 13

Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/step-by-step-walkthrough: metric framing, mechanism proof, hardware implications, and release safety.

Evidence checklist

• Metric context includes workload, dataset slice, and revision tags.

• Mechanism explanation links model behavior to observed outcome.

• Hardware/runtime feasibility is profiled, not assumed.

• Owner and rollback path are documented before rollout.

Review prompts

1. Which decision will this model output influence?

2. What is the first failing layer when metric regresses?

3. Which owner applies the smallest reversible fix?

4. What validation matrix is required before deployment?

Evidence capsule

AI-VLSI EVIDENCE CAPSULE 13

PATH: ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/step-by-step-walkthrough
WORKLOAD SLICE: <name>
PRIMARY METRIC: <value/trend>
FIRST FAILING LAYER: <data/model/runtime/hardware>
OWNER: <name>
PRIMARY ARTIFACT: <report/profile/dashboard>
DECISION: <ship / rollback / escalate>

Principal AI-VLSI review addendum

Systolic and related MAC array organizations maximize reuse and throughput when data movement is orchestrated with regular flow patterns.

Metric: array utilization, stall ratio, and TOPS/mm2 estimate