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Course contents

  • How to Use This Course
  • AI-VLSI Metrics Reference
  • AI-VLSI Glossary
  • Reading Path
  • ML Math Foundations61
  • Neural Networks Basics61
  • Training Data Pipeline61
  • AI Compute Hardware61
    • CPU, GPU, TPU, NPU Landscape
    • Memory Bandwidth & Roofline
    • Precision & Quantization
    • Inference vs Training Silicon
    • AI Compute Hardware: Tricky Q&A
  • Accelerator Architecture61
  • AI in VLSI Workflows61
  • Edge Deployment & MLOps61
  • AI-VLSI Interview Prep4
  • AI Basics for VLSI Engineers Cheatsheet
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‹AI for VLSI
  1. Topics
  2. AI for VLSI
  3. AI Compute Hardware

AI for VLSI · All levels

AI Compute Hardware

Compute platform landscape, roofline constraints, precision tradeoffs, and silicon differences between training and inference.

  • 5topics
  • 61lessons

Topics in this section

  1. 1CPU, GPU, TPU, NPU Landscape15 lessons
    • CPU, GPU, TPU, NPU Landscape: Mechanism
    • CPU, GPU, TPU, NPU Landscape: Inputs & Outputs
    • CPU, GPU, TPU, NPU Landscape: Reports & Metrics
    • CPU, GPU, TPU, NPU Landscape: Debug Playbook
    • CPU, GPU, TPU, NPU Landscape: Worked Example
    • CPU, GPU, TPU, NPU Landscape: Pitfalls & Red Flags
    • CPU, GPU, TPU, NPU Landscape: Interview Drills
    • CPU, GPU, TPU, NPU Landscape: Review Checklist
    • CPU, GPU, TPU, NPU Landscape: Theory Deep Dive
    • CPU, GPU, TPU, NPU Landscape: Design Space
    • CPU, GPU, TPU, NPU Landscape: Expanded Case Study
    • CPU, GPU, TPU, NPU Landscape: Step-by-Step Walkthrough
    • CPU, GPU, TPU, NPU Landscape: Comparison Matrix
    • CPU, GPU, TPU, NPU Landscape: Software / Programmer View
    • CPU, GPU, TPU, NPU Landscape: Silicon PPA Impact
  2. 2Memory Bandwidth & Roofline15 lessons
    • Memory Bandwidth & Roofline: Mechanism
    • Memory Bandwidth & Roofline: Inputs & Outputs
    • Memory Bandwidth & Roofline: Reports & Metrics
    • Memory Bandwidth & Roofline: Debug Playbook
    • Memory Bandwidth & Roofline: Worked Example
    • Memory Bandwidth & Roofline: Pitfalls & Red Flags
    • Memory Bandwidth & Roofline: Interview Drills
    • Memory Bandwidth & Roofline: Review Checklist
    • Memory Bandwidth & Roofline: Theory Deep Dive
    • Memory Bandwidth & Roofline: Design Space
    • Memory Bandwidth & Roofline: Expanded Case Study
    • Memory Bandwidth & Roofline: Step-by-Step Walkthrough
    • Memory Bandwidth & Roofline: Comparison Matrix
    • Memory Bandwidth & Roofline: Software / Programmer View
    • Memory Bandwidth & Roofline: Silicon PPA Impact
  3. 3Precision & Quantization15 lessons
    • Precision & Quantization: Mechanism
    • Precision & Quantization: Inputs & Outputs
    • Precision & Quantization: Reports & Metrics
    • Precision & Quantization: Debug Playbook
    • Precision & Quantization: Worked Example
    • Precision & Quantization: Pitfalls & Red Flags
    • Precision & Quantization: Interview Drills
    • Precision & Quantization: Review Checklist
    • Precision & Quantization: Theory Deep Dive
    • Precision & Quantization: Design Space
    • Precision & Quantization: Expanded Case Study
    • Precision & Quantization: Step-by-Step Walkthrough
    • Precision & Quantization: Comparison Matrix
    • Precision & Quantization: Software / Programmer View
    • Precision & Quantization: Silicon PPA Impact
  4. 4Inference vs Training Silicon15 lessons
    • Inference vs Training Silicon: Mechanism
    • Inference vs Training Silicon: Inputs & Outputs
    • Inference vs Training Silicon: Reports & Metrics
    • Inference vs Training Silicon: Debug Playbook
    • Inference vs Training Silicon: Worked Example
    • Inference vs Training Silicon: Pitfalls & Red Flags
    • Inference vs Training Silicon: Interview Drills
    • Inference vs Training Silicon: Review Checklist
    • Inference vs Training Silicon: Theory Deep Dive
    • Inference vs Training Silicon: Design Space
    • Inference vs Training Silicon: Expanded Case Study
    • Inference vs Training Silicon: Step-by-Step Walkthrough
    • Inference vs Training Silicon: Comparison Matrix
    • Inference vs Training Silicon: Software / Programmer View
    • Inference vs Training Silicon: Silicon PPA Impact
  5. 5AI Compute Hardware: Tricky Q&A1 lesson
On this page

    Section goal

    Compute platform landscape, roofline constraints, precision tradeoffs, and silicon differences between training and inference.

    How to study this section

    1. Start with each topic hub and sketch the data-model-hardware contract.

    2. Use mechanism and reports pages to connect metrics to decisions.

    3. Practice debug and worked-example pages for review readiness.

    4. Close with checklist and silicon impact before deployment decisions.

    Topics

    1. cpu-gpu-tpu-npu-landscape/ — CPU, GPU, TPU, NPU Landscape

    2. memory-bandwidth-and-roofline/ — Memory Bandwidth & Roofline

    3. precision-and-quantization/ — Precision & Quantization

    4. inference-vs-training-silicon/ — Inference vs Training Silicon

    Related topics

    • AI for VLSI course hub

    AI-VLSI deep dive

    Throughput claims are meaningless without roofline and bandwidth context.

    Concept diagram

    Diagram
    COMPUTE ANALYSIS
    
    workload profile -> roofline -> precision policy -> target silicon

    Metric graph

    Diagram
    EFFICIENCY DRIVERS
    
    compute utilization    ██████
    memory utilization     █████████
    precision efficiency   ███████

    Reports and artifacts

    • platform benchmark matrix

    • roofline chart

    • precision sweep

    • latency/power dashboard

    Mini case study

    Kernel optimization shifted from compute tuning to memory tiling after roofline analysis.

    Debug branches

    • Classify compute vs memory bound

    • Compare precision tiers

    • Align platform to SLA

    Senior review question

    Ask: what evidence connects this ML claim to a concrete VLSI workflow decision and owner signoff?

    Execution drill pack 1

    Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/ai-compute-hardware: metric framing, mechanism proof, hardware implications, and release safety.

    Evidence checklist

    • Metric context includes workload, dataset slice, and revision tags.

    • Mechanism explanation links model behavior to observed outcome.

    • Hardware/runtime feasibility is profiled, not assumed.

    • Owner and rollback path are documented before rollout.

    Review prompts

    1. Which decision will this model output influence?

    2. What is the first failing layer when metric regresses?

    3. Which owner applies the smallest reversible fix?

    4. What validation matrix is required before deployment?

    Evidence capsule

    Diagram
    AI-VLSI EVIDENCE CAPSULE 1
    
    PATH: ai-vlsi/ai-compute-hardware
    WORKLOAD SLICE: <name>
    PRIMARY METRIC: <value/trend>
    FIRST FAILING LAYER: <data/model/runtime/hardware>
    OWNER: <name>
    PRIMARY ARTIFACT: <report/profile/dashboard>
    DECISION: <ship / rollback / escalate>

    Execution drill pack 2

    Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/ai-compute-hardware: metric framing, mechanism proof, hardware implications, and release safety.

    Evidence checklist

    • Metric context includes workload, dataset slice, and revision tags.

    • Mechanism explanation links model behavior to observed outcome.

    • Hardware/runtime feasibility is profiled, not assumed.

    • Owner and rollback path are documented before rollout.

    Review prompts

    1. Which decision will this model output influence?

    2. What is the first failing layer when metric regresses?

    3. Which owner applies the smallest reversible fix?

    4. What validation matrix is required before deployment?

    Evidence capsule

    Diagram
    AI-VLSI EVIDENCE CAPSULE 2
    
    PATH: ai-vlsi/ai-compute-hardware
    WORKLOAD SLICE: <name>
    PRIMARY METRIC: <value/trend>
    FIRST FAILING LAYER: <data/model/runtime/hardware>
    OWNER: <name>
    PRIMARY ARTIFACT: <report/profile/dashboard>
    DECISION: <ship / rollback / escalate>

    Execution drill pack 3

    Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/ai-compute-hardware: metric framing, mechanism proof, hardware implications, and release safety.

    Evidence checklist

    • Metric context includes workload, dataset slice, and revision tags.

    • Mechanism explanation links model behavior to observed outcome.

    • Hardware/runtime feasibility is profiled, not assumed.

    • Owner and rollback path are documented before rollout.

    Review prompts

    1. Which decision will this model output influence?

    2. What is the first failing layer when metric regresses?

    3. Which owner applies the smallest reversible fix?

    4. What validation matrix is required before deployment?

    Evidence capsule

    Diagram
    AI-VLSI EVIDENCE CAPSULE 3
    
    PATH: ai-vlsi/ai-compute-hardware
    WORKLOAD SLICE: <name>
    PRIMARY METRIC: <value/trend>
    FIRST FAILING LAYER: <data/model/runtime/hardware>
    OWNER: <name>
    PRIMARY ARTIFACT: <report/profile/dashboard>
    DECISION: <ship / rollback / escalate>

    Execution drill pack 4

    Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/ai-compute-hardware: metric framing, mechanism proof, hardware implications, and release safety.

    Evidence checklist

    • Metric context includes workload, dataset slice, and revision tags.

    • Mechanism explanation links model behavior to observed outcome.

    • Hardware/runtime feasibility is profiled, not assumed.

    • Owner and rollback path are documented before rollout.

    Review prompts

    1. Which decision will this model output influence?

    2. What is the first failing layer when metric regresses?

    3. Which owner applies the smallest reversible fix?

    4. What validation matrix is required before deployment?

    Evidence capsule

    Diagram
    AI-VLSI EVIDENCE CAPSULE 4
    
    PATH: ai-vlsi/ai-compute-hardware
    WORKLOAD SLICE: <name>
    PRIMARY METRIC: <value/trend>
    FIRST FAILING LAYER: <data/model/runtime/hardware>
    OWNER: <name>
    PRIMARY ARTIFACT: <report/profile/dashboard>
    DECISION: <ship / rollback / escalate>

    Execution drill pack 5

    Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/ai-compute-hardware: metric framing, mechanism proof, hardware implications, and release safety.

    Evidence checklist

    • Metric context includes workload, dataset slice, and revision tags.

    • Mechanism explanation links model behavior to observed outcome.

    • Hardware/runtime feasibility is profiled, not assumed.

    • Owner and rollback path are documented before rollout.

    Review prompts

    1. Which decision will this model output influence?

    2. What is the first failing layer when metric regresses?

    3. Which owner applies the smallest reversible fix?

    4. What validation matrix is required before deployment?

    Evidence capsule

    Diagram
    AI-VLSI EVIDENCE CAPSULE 5
    
    PATH: ai-vlsi/ai-compute-hardware
    WORKLOAD SLICE: <name>
    PRIMARY METRIC: <value/trend>
    FIRST FAILING LAYER: <data/model/runtime/hardware>
    OWNER: <name>
    PRIMARY ARTIFACT: <report/profile/dashboard>
    DECISION: <ship / rollback / escalate>
    PreviousNext: CPU, GPU, TPU, NPU Landscape

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    See also

    • How to Use This Course
    • AI-VLSI Metrics Reference
    • AI-VLSI Glossary