Memory Bandwidth & Roofline turns AI concepts into VLSI-ready engineering decisions. Roofline analysis links arithmetic intensity to memory bandwidth limits, exposing whether kernels are compute-bound or memory-bound. The practical challenge is proving value with reproducible evidence, bounded risk, and explicit ownership.
When operational intensity, achieved TOPS, and bandwidth utilization moves, can you identify the failing layer, the mechanism, the artifact, and the owner who can close risk with a measurable fix?
AI-VLSI FLOW — Memory Bandwidth & Roofline
problem framing
|
v
data + model definition
|
v
training / optimization
|
v
compute-hardware mapping
|
v
deployment + validation
Primary metric: operational intensity, achieved TOPS, and bandwidth utilizationStart each review with an architecture sketch before opening dashboards. These diagrams are designed for design reviews and interview whiteboards.
ROOFLINE
performance
^
| compute ceiling
| /
| /
|---/---------------- memory ceiling
+--------------------> operational intensity
Low intensity kernels are bandwidth-bound.TENSOR / PIPELINE MAP — Memory Bandwidth & Roofline
feature source -> preprocessing -> tensorized input
| |
+---- shape + scale checks ---+
|
v
model execution / inference
Shape and scaling discipline decides correctness and portability.TRAINING TIMELINE — Memory Bandwidth & Roofline
time --->
data batch __/--/--/--/--/--/--/--
forward pass ____/--/--/--/--/--/---
backward pass ________/--/--/--/-----
optimizer step ____________/--/--/----
eval checkpoint _____________/--/-------
Convergence depends on stable loop timing and signal quality.ROOFLINE LENS — Memory Bandwidth & Roofline
performance
^
| compute bound region
| /
| /
|-------------/---------------- memory bound region
+----------------------------------------------> operational intensity
Use this to decide compute optimization vs memory optimization.AI-VLSI OWNERSHIP LAYERS — Memory Bandwidth & Roofline
layer owns typical failure
--------------------- -------------------------------- ----------------------------
problem framing metric + acceptance criteria wrong objective target
model + training representation + optimization unstable or biased model
hardware mapping dataflow + memory + precision bandwidth stalls / mismatch
deployment stack runtime + firmware + drivers latency jitter / incompatibility
governance monitoring + rollback + signoff silent drift in productionPrimary metric: operational intensity, achieved TOPS, and bandwidth utilization.
Primary artifact: roofline plot, kernel profile report, and memory traffic breakdown.
Owners to bring into review: performance engineer, compiler owner, accelerator architect.
One workload slice where behavior regressed and one where it held.
One profile view that separates model issue from runtime/hardware issue.
OWNERSHIP MAP — Memory Bandwidth & Roofline
artifact focus owner
------------------ ----------------------------
modeling performance engineer
architecture compiler owner
integration accelerator architect
Production issues happen when ownership is assumed, not declared.Each topic is taught across mechanism, inputs/outputs, reports, debug, worked example, pitfalls, interview, checklist, theory, design space, expanded case study, walkthrough, comparison matrix, software view, and silicon impact.
Always map ML metrics to engineering decisions and release risk.
Separate data/model issues from hardware/runtime bottlenecks before fixing.
Use reproducible artifacts and owner signoff for every rollout decision.
Benchmark wins with no signoff correlation.
Ignoring calibration and drift when deploying quantized models.
Shipping without a rollback and ownership matrix.
Throughput claims are meaningless without roofline and bandwidth context.
COMPUTE ANALYSIS
workload profile -> roofline -> precision policy -> target siliconEFFICIENCY DRIVERS
compute utilization ██████
memory utilization █████████
precision efficiency ███████platform benchmark matrix
roofline chart
precision sweep
latency/power dashboard
Kernel optimization shifted from compute tuning to memory tiling after roofline analysis.
Classify compute vs memory bound
Compare precision tiers
Align platform to SLA
Ask: what evidence connects this ML claim to a concrete VLSI workflow decision and owner signoff?
Every AI claim should map to a measurable engineering outcome.
Validate both model quality and hardware/runtime feasibility before adoption.
Optimizing benchmark metrics that do not correlate with signoff goals.
Ignoring data drift and calibration after deployment.
Shipping ML workflows without clear rollback ownership.
Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/ai-compute-hardware/memory-bandwidth-and-roofline: metric framing, mechanism proof, hardware implications, and release safety.
Metric context includes workload, dataset slice, and revision tags.
Mechanism explanation links model behavior to observed outcome.
Hardware/runtime feasibility is profiled, not assumed.
Owner and rollback path are documented before rollout.
Which decision will this model output influence?
What is the first failing layer when metric regresses?
Which owner applies the smallest reversible fix?
What validation matrix is required before deployment?
AI-VLSI EVIDENCE CAPSULE 1
PATH: ai-vlsi/ai-compute-hardware/memory-bandwidth-and-roofline
WORKLOAD SLICE: <name>
PRIMARY METRIC: <value/trend>
FIRST FAILING LAYER: <data/model/runtime/hardware>
OWNER: <name>
PRIMARY ARTIFACT: <report/profile/dashboard>
DECISION: <ship / rollback / escalate>Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/ai-compute-hardware/memory-bandwidth-and-roofline: metric framing, mechanism proof, hardware implications, and release safety.
Metric context includes workload, dataset slice, and revision tags.
Mechanism explanation links model behavior to observed outcome.
Hardware/runtime feasibility is profiled, not assumed.
Owner and rollback path are documented before rollout.
Which decision will this model output influence?
What is the first failing layer when metric regresses?
Which owner applies the smallest reversible fix?
What validation matrix is required before deployment?
AI-VLSI EVIDENCE CAPSULE 2
PATH: ai-vlsi/ai-compute-hardware/memory-bandwidth-and-roofline
WORKLOAD SLICE: <name>
PRIMARY METRIC: <value/trend>
FIRST FAILING LAYER: <data/model/runtime/hardware>
OWNER: <name>
PRIMARY ARTIFACT: <report/profile/dashboard>
DECISION: <ship / rollback / escalate>Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/ai-compute-hardware/memory-bandwidth-and-roofline: metric framing, mechanism proof, hardware implications, and release safety.
Metric context includes workload, dataset slice, and revision tags.
Mechanism explanation links model behavior to observed outcome.
Hardware/runtime feasibility is profiled, not assumed.
Owner and rollback path are documented before rollout.
Which decision will this model output influence?
What is the first failing layer when metric regresses?
Which owner applies the smallest reversible fix?
What validation matrix is required before deployment?
AI-VLSI EVIDENCE CAPSULE 3
PATH: ai-vlsi/ai-compute-hardware/memory-bandwidth-and-roofline
WORKLOAD SLICE: <name>
PRIMARY METRIC: <value/trend>
FIRST FAILING LAYER: <data/model/runtime/hardware>
OWNER: <name>
PRIMARY ARTIFACT: <report/profile/dashboard>
DECISION: <ship / rollback / escalate>Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/ai-compute-hardware/memory-bandwidth-and-roofline: metric framing, mechanism proof, hardware implications, and release safety.
Metric context includes workload, dataset slice, and revision tags.
Mechanism explanation links model behavior to observed outcome.
Hardware/runtime feasibility is profiled, not assumed.
Owner and rollback path are documented before rollout.
Which decision will this model output influence?
What is the first failing layer when metric regresses?
Which owner applies the smallest reversible fix?
What validation matrix is required before deployment?
AI-VLSI EVIDENCE CAPSULE 4
PATH: ai-vlsi/ai-compute-hardware/memory-bandwidth-and-roofline
WORKLOAD SLICE: <name>
PRIMARY METRIC: <value/trend>
FIRST FAILING LAYER: <data/model/runtime/hardware>
OWNER: <name>
PRIMARY ARTIFACT: <report/profile/dashboard>
DECISION: <ship / rollback / escalate>Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/ai-compute-hardware/memory-bandwidth-and-roofline: metric framing, mechanism proof, hardware implications, and release safety.
Metric context includes workload, dataset slice, and revision tags.
Mechanism explanation links model behavior to observed outcome.
Hardware/runtime feasibility is profiled, not assumed.
Owner and rollback path are documented before rollout.
Which decision will this model output influence?
What is the first failing layer when metric regresses?
Which owner applies the smallest reversible fix?
What validation matrix is required before deployment?
AI-VLSI EVIDENCE CAPSULE 5
PATH: ai-vlsi/ai-compute-hardware/memory-bandwidth-and-roofline
WORKLOAD SLICE: <name>
PRIMARY METRIC: <value/trend>
FIRST FAILING LAYER: <data/model/runtime/hardware>
OWNER: <name>
PRIMARY ARTIFACT: <report/profile/dashboard>
DECISION: <ship / rollback / escalate>Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/ai-compute-hardware/memory-bandwidth-and-roofline: metric framing, mechanism proof, hardware implications, and release safety.
Metric context includes workload, dataset slice, and revision tags.
Mechanism explanation links model behavior to observed outcome.
Hardware/runtime feasibility is profiled, not assumed.
Owner and rollback path are documented before rollout.
Which decision will this model output influence?
What is the first failing layer when metric regresses?
Which owner applies the smallest reversible fix?
What validation matrix is required before deployment?
AI-VLSI EVIDENCE CAPSULE 6
PATH: ai-vlsi/ai-compute-hardware/memory-bandwidth-and-roofline
WORKLOAD SLICE: <name>
PRIMARY METRIC: <value/trend>
FIRST FAILING LAYER: <data/model/runtime/hardware>
OWNER: <name>
PRIMARY ARTIFACT: <report/profile/dashboard>
DECISION: <ship / rollback / escalate>Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/ai-compute-hardware/memory-bandwidth-and-roofline: metric framing, mechanism proof, hardware implications, and release safety.
Metric context includes workload, dataset slice, and revision tags.
Mechanism explanation links model behavior to observed outcome.
Hardware/runtime feasibility is profiled, not assumed.
Owner and rollback path are documented before rollout.
Which decision will this model output influence?
What is the first failing layer when metric regresses?
Which owner applies the smallest reversible fix?
What validation matrix is required before deployment?
AI-VLSI EVIDENCE CAPSULE 7
PATH: ai-vlsi/ai-compute-hardware/memory-bandwidth-and-roofline
WORKLOAD SLICE: <name>
PRIMARY METRIC: <value/trend>
FIRST FAILING LAYER: <data/model/runtime/hardware>
OWNER: <name>
PRIMARY ARTIFACT: <report/profile/dashboard>
DECISION: <ship / rollback / escalate>