AI for VLSI · All levels

Memory Bandwidth & Roofline

AI Compute Hardware: Roofline analysis links arithmetic intensity to memory bandwidth limits, exposing whether kernels are compute-bound or memory-bound.

What this topic teaches

Memory Bandwidth & Roofline turns AI concepts into VLSI-ready engineering decisions. Roofline analysis links arithmetic intensity to memory bandwidth limits, exposing whether kernels are compute-bound or memory-bound. The practical challenge is proving value with reproducible evidence, bounded risk, and explicit ownership.

The senior-engineer question

When operational intensity, achieved TOPS, and bandwidth utilization moves, can you identify the failing layer, the mechanism, the artifact, and the owner who can close risk with a measurable fix?

diagram

AI-VLSI FLOW — Memory Bandwidth & Roofline

problem framing
      |
      v
data + model definition
      |
      v
training / optimization
      |
      v
compute-hardware mapping
      |
      v
deployment + validation

Primary metric: operational intensity, achieved TOPS, and bandwidth utilization

Picture the system

Start each review with an architecture sketch before opening dashboards. These diagrams are designed for design reviews and interview whiteboards.

Roofline interpretation

diagram

ROOFLINE

performance
   ^
   |      compute ceiling
   |     /
   |    /
   |---/---------------- memory ceiling
   +--------------------> operational intensity

Low intensity kernels are bandwidth-bound.

Tensor and data path

diagram

TENSOR / PIPELINE MAP — Memory Bandwidth & Roofline

feature source -> preprocessing -> tensorized input
      |                             |
      +---- shape + scale checks ---+
                    |
                    v
            model execution / inference

Shape and scaling discipline decides correctness and portability.

Training and update loop

diagram

TRAINING TIMELINE — Memory Bandwidth & Roofline

time --->
data batch      __/--/--/--/--/--/--/--
forward pass    ____/--/--/--/--/--/---
backward pass   ________/--/--/--/-----
optimizer step  ____________/--/--/----
eval checkpoint _____________/--/-------

Convergence depends on stable loop timing and signal quality.

Compute limit lens

diagram

ROOFLINE LENS — Memory Bandwidth & Roofline

performance
   ^
   |                compute bound region
   |               /
   |              /
   |-------------/---------------- memory bound region
   +----------------------------------------------> operational intensity

Use this to decide compute optimization vs memory optimization.

Ownership layers

diagram

AI-VLSI OWNERSHIP LAYERS — Memory Bandwidth & Roofline

layer                    owns                               typical failure
---------------------    --------------------------------   ----------------------------
problem framing          metric + acceptance criteria       wrong objective target
model + training         representation + optimization      unstable or biased model
hardware mapping         dataflow + memory + precision      bandwidth stalls / mismatch
deployment stack         runtime + firmware + drivers       latency jitter / incompatibility
governance               monitoring + rollback + signoff    silent drift in production

Evidence to collect

Primary metric: operational intensity, achieved TOPS, and bandwidth utilization.
Primary artifact: roofline plot, kernel profile report, and memory traffic breakdown.
Owners to bring into review: performance engineer, compiler owner, accelerator architect.
One workload slice where behavior regressed and one where it held.
One profile view that separates model issue from runtime/hardware issue.

Ownership map

diagram

OWNERSHIP MAP — Memory Bandwidth & Roofline

artifact focus         owner
------------------     ----------------------------
modeling          performance engineer
architecture      compiler owner
integration       accelerator architect

Production issues happen when ownership is assumed, not declared.

Subpages in this topic

Each topic is taught across mechanism, inputs/outputs, reports, debug, worked example, pitfalls, interview, checklist, theory, design space, expanded case study, walkthrough, comparison matrix, software view, and silicon impact.

Key takeaways

Always map ML metrics to engineering decisions and release risk.
Separate data/model issues from hardware/runtime bottlenecks before fixing.
Use reproducible artifacts and owner signoff for every rollout decision.

Common pitfalls

Benchmark wins with no signoff correlation.
Ignoring calibration and drift when deploying quantized models.
Shipping without a rollback and ownership matrix.

AI-VLSI deep dive

Throughput claims are meaningless without roofline and bandwidth context.

Concept diagram

diagram

COMPUTE ANALYSIS

workload profile -> roofline -> precision policy -> target silicon

Metric graph

diagram

EFFICIENCY DRIVERS

compute utilization    ██████
memory utilization     █████████
precision efficiency   ███████

Reports and artifacts

platform benchmark matrix
roofline chart
precision sweep
latency/power dashboard

Mini case study

Kernel optimization shifted from compute tuning to memory tiling after roofline analysis.

Debug branches

Classify compute vs memory bound
Compare precision tiers
Align platform to SLA

Senior review question

Ask: what evidence connects this ML claim to a concrete VLSI workflow decision and owner signoff?

Key takeaways

Every AI claim should map to a measurable engineering outcome.
Validate both model quality and hardware/runtime feasibility before adoption.

Common pitfalls

Optimizing benchmark metrics that do not correlate with signoff goals.
Ignoring data drift and calibration after deployment.
Shipping ML workflows without clear rollback ownership.

Execution drill pack 1

Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/ai-compute-hardware/memory-bandwidth-and-roofline: metric framing, mechanism proof, hardware implications, and release safety.

Evidence checklist

Metric context includes workload, dataset slice, and revision tags.
Mechanism explanation links model behavior to observed outcome.
Hardware/runtime feasibility is profiled, not assumed.
Owner and rollback path are documented before rollout.

Review prompts

Which decision will this model output influence?
What is the first failing layer when metric regresses?
Which owner applies the smallest reversible fix?
What validation matrix is required before deployment?

Evidence capsule

diagram

AI-VLSI EVIDENCE CAPSULE 1

PATH: ai-vlsi/ai-compute-hardware/memory-bandwidth-and-roofline
WORKLOAD SLICE: <name>
PRIMARY METRIC: <value/trend>
FIRST FAILING LAYER: <data/model/runtime/hardware>
OWNER: <name>
PRIMARY ARTIFACT: <report/profile/dashboard>
DECISION: <ship / rollback / escalate>

Execution drill pack 2

Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/ai-compute-hardware/memory-bandwidth-and-roofline: metric framing, mechanism proof, hardware implications, and release safety.

Evidence checklist

Metric context includes workload, dataset slice, and revision tags.
Mechanism explanation links model behavior to observed outcome.
Hardware/runtime feasibility is profiled, not assumed.
Owner and rollback path are documented before rollout.

Review prompts

Which decision will this model output influence?
What is the first failing layer when metric regresses?
Which owner applies the smallest reversible fix?
What validation matrix is required before deployment?

Evidence capsule

diagram

AI-VLSI EVIDENCE CAPSULE 2

PATH: ai-vlsi/ai-compute-hardware/memory-bandwidth-and-roofline
WORKLOAD SLICE: <name>
PRIMARY METRIC: <value/trend>
FIRST FAILING LAYER: <data/model/runtime/hardware>
OWNER: <name>
PRIMARY ARTIFACT: <report/profile/dashboard>
DECISION: <ship / rollback / escalate>

Execution drill pack 3

Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/ai-compute-hardware/memory-bandwidth-and-roofline: metric framing, mechanism proof, hardware implications, and release safety.

Evidence checklist

Metric context includes workload, dataset slice, and revision tags.
Mechanism explanation links model behavior to observed outcome.
Hardware/runtime feasibility is profiled, not assumed.
Owner and rollback path are documented before rollout.

Review prompts

Which decision will this model output influence?
What is the first failing layer when metric regresses?
Which owner applies the smallest reversible fix?
What validation matrix is required before deployment?

Evidence capsule

diagram

AI-VLSI EVIDENCE CAPSULE 3

PATH: ai-vlsi/ai-compute-hardware/memory-bandwidth-and-roofline
WORKLOAD SLICE: <name>
PRIMARY METRIC: <value/trend>
FIRST FAILING LAYER: <data/model/runtime/hardware>
OWNER: <name>
PRIMARY ARTIFACT: <report/profile/dashboard>
DECISION: <ship / rollback / escalate>

Execution drill pack 4

Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/ai-compute-hardware/memory-bandwidth-and-roofline: metric framing, mechanism proof, hardware implications, and release safety.

Evidence checklist

Metric context includes workload, dataset slice, and revision tags.
Mechanism explanation links model behavior to observed outcome.
Hardware/runtime feasibility is profiled, not assumed.
Owner and rollback path are documented before rollout.

Review prompts

Which decision will this model output influence?
What is the first failing layer when metric regresses?
Which owner applies the smallest reversible fix?
What validation matrix is required before deployment?

Evidence capsule

diagram

AI-VLSI EVIDENCE CAPSULE 4

PATH: ai-vlsi/ai-compute-hardware/memory-bandwidth-and-roofline
WORKLOAD SLICE: <name>
PRIMARY METRIC: <value/trend>
FIRST FAILING LAYER: <data/model/runtime/hardware>
OWNER: <name>
PRIMARY ARTIFACT: <report/profile/dashboard>
DECISION: <ship / rollback / escalate>

Execution drill pack 5

Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/ai-compute-hardware/memory-bandwidth-and-roofline: metric framing, mechanism proof, hardware implications, and release safety.

Evidence checklist

Metric context includes workload, dataset slice, and revision tags.
Mechanism explanation links model behavior to observed outcome.
Hardware/runtime feasibility is profiled, not assumed.
Owner and rollback path are documented before rollout.

Review prompts

Which decision will this model output influence?
What is the first failing layer when metric regresses?
Which owner applies the smallest reversible fix?
What validation matrix is required before deployment?

Evidence capsule

diagram

AI-VLSI EVIDENCE CAPSULE 5

PATH: ai-vlsi/ai-compute-hardware/memory-bandwidth-and-roofline
WORKLOAD SLICE: <name>
PRIMARY METRIC: <value/trend>
FIRST FAILING LAYER: <data/model/runtime/hardware>
OWNER: <name>
PRIMARY ARTIFACT: <report/profile/dashboard>
DECISION: <ship / rollback / escalate>

Execution drill pack 6

Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/ai-compute-hardware/memory-bandwidth-and-roofline: metric framing, mechanism proof, hardware implications, and release safety.

Evidence checklist

Metric context includes workload, dataset slice, and revision tags.
Mechanism explanation links model behavior to observed outcome.
Hardware/runtime feasibility is profiled, not assumed.
Owner and rollback path are documented before rollout.

Review prompts

Which decision will this model output influence?
What is the first failing layer when metric regresses?
Which owner applies the smallest reversible fix?
What validation matrix is required before deployment?

Evidence capsule

diagram

AI-VLSI EVIDENCE CAPSULE 6

PATH: ai-vlsi/ai-compute-hardware/memory-bandwidth-and-roofline
WORKLOAD SLICE: <name>
PRIMARY METRIC: <value/trend>
FIRST FAILING LAYER: <data/model/runtime/hardware>
OWNER: <name>
PRIMARY ARTIFACT: <report/profile/dashboard>
DECISION: <ship / rollback / escalate>

Execution drill pack 7

Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/ai-compute-hardware/memory-bandwidth-and-roofline: metric framing, mechanism proof, hardware implications, and release safety.

Evidence checklist

Metric context includes workload, dataset slice, and revision tags.
Mechanism explanation links model behavior to observed outcome.
Hardware/runtime feasibility is profiled, not assumed.
Owner and rollback path are documented before rollout.

Review prompts

Which decision will this model output influence?
What is the first failing layer when metric regresses?
Which owner applies the smallest reversible fix?
What validation matrix is required before deployment?

Evidence capsule

diagram

AI-VLSI EVIDENCE CAPSULE 7

PATH: ai-vlsi/ai-compute-hardware/memory-bandwidth-and-roofline
WORKLOAD SLICE: <name>
PRIMARY METRIC: <value/trend>
FIRST FAILING LAYER: <data/model/runtime/hardware>
OWNER: <name>
PRIMARY ARTIFACT: <report/profile/dashboard>
DECISION: <ship / rollback / escalate>

Practice this lesson