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MAC Arrays & Systolic: Worked Example

Worked Example for MAC Arrays & Systolic.

Worked example

Worked Example for MAC Arrays & Systolic focuses on array utilization, stall ratio, and TOPS/mm2 estimate. The goal is to connect model behavior to hardware-aware decisions and operational risk.

A release check flags array utilization, stall ratio, and TOPS/mm2 estimate. Correct triage freezes revision tags, identifies failing layer, and validates one bounded fix before broad rollout.

System sketch under review

diagram
AI-VLSI FLOW — MAC Arrays & Systolic

problem framing
      |
      v
data + model definition
      |
      v
training / optimization
      |
      v
compute-hardware mapping
      |
      v
deployment + validation

Primary metric: array utilization, stall ratio, and TOPS/mm2 estimate

Systolic data movement

diagram
SYSTOLIC ARRAY

inputs stream horizontally
weights stream vertically
partial sums accumulate in PEs

Utilization depends on tile shape + scheduling.

  1. Capture failing workload and baseline comparator.

  2. Record data/model/runtime/hardware revision tags.

  3. Compare expected vs observed behavior on one focused slice.

  4. Collect array mapping sheet, utilization report, and cycle-accurate trace.

  5. Apply one reversible fix and define rollback before rollout.

Did the fix hold?

diagram
BEFORE / AFTER — MAC Arrays & Systolic

metric quality
  ^
  |                        o target region
  |                 o post-fix + regression
  |            o
  |      o baseline failing run
  +-----------------------------------------> iteration
      evidence audit   fix    full validation

AI-VLSI deep dive

Dataflow and memory hierarchy choices dominate practical accelerator performance.

Concept diagram

diagram
ACCELERATOR STACK

MAC array -> dataflow map -> SRAM hierarchy -> NoC/DRAM

Metric graph

diagram
BOTTLENECK MIX

array underutilization ████
SRAM pressure          ███████
NoC/DRAM congestion    ██████

Reports and artifacts

  • array utilization

  • reuse factor report

  • buffer hit analysis

  • NoC/DRAM bottleneck trace

Mini case study

A dataflow change improved reuse but exposed NoC congestion, requiring route-policy updates.

Debug branches

  • Map reuse factors

  • Inspect memory stall sources

  • Profile NoC arbitration

Senior review question

Ask: what evidence connects this ML claim to a concrete VLSI workflow decision and owner signoff?

Key takeaways

  • Every AI claim should map to a measurable engineering outcome.

  • Validate both model quality and hardware/runtime feasibility before adoption.

Common pitfalls

  • Optimizing benchmark metrics that do not correlate with signoff goals.

  • Ignoring data drift and calibration after deployment.

  • Shipping ML workflows without clear rollback ownership.

Execution drill pack 1

Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/worked-example: metric framing, mechanism proof, hardware implications, and release safety.

Evidence checklist

  • Metric context includes workload, dataset slice, and revision tags.

  • Mechanism explanation links model behavior to observed outcome.

  • Hardware/runtime feasibility is profiled, not assumed.

  • Owner and rollback path are documented before rollout.

Review prompts

  1. Which decision will this model output influence?

  2. What is the first failing layer when metric regresses?

  3. Which owner applies the smallest reversible fix?

  4. What validation matrix is required before deployment?

Evidence capsule

diagram
AI-VLSI EVIDENCE CAPSULE 1

PATH: ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/worked-example
WORKLOAD SLICE: <name>
PRIMARY METRIC: <value/trend>
FIRST FAILING LAYER: <data/model/runtime/hardware>
OWNER: <name>
PRIMARY ARTIFACT: <report/profile/dashboard>
DECISION: <ship / rollback / escalate>

Execution drill pack 2

Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/worked-example: metric framing, mechanism proof, hardware implications, and release safety.

Evidence checklist

  • Metric context includes workload, dataset slice, and revision tags.

  • Mechanism explanation links model behavior to observed outcome.

  • Hardware/runtime feasibility is profiled, not assumed.

  • Owner and rollback path are documented before rollout.

Review prompts

  1. Which decision will this model output influence?

  2. What is the first failing layer when metric regresses?

  3. Which owner applies the smallest reversible fix?

  4. What validation matrix is required before deployment?

Evidence capsule

diagram
AI-VLSI EVIDENCE CAPSULE 2

PATH: ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/worked-example
WORKLOAD SLICE: <name>
PRIMARY METRIC: <value/trend>
FIRST FAILING LAYER: <data/model/runtime/hardware>
OWNER: <name>
PRIMARY ARTIFACT: <report/profile/dashboard>
DECISION: <ship / rollback / escalate>

Execution drill pack 3

Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/worked-example: metric framing, mechanism proof, hardware implications, and release safety.

Evidence checklist

  • Metric context includes workload, dataset slice, and revision tags.

  • Mechanism explanation links model behavior to observed outcome.

  • Hardware/runtime feasibility is profiled, not assumed.

  • Owner and rollback path are documented before rollout.

Review prompts

  1. Which decision will this model output influence?

  2. What is the first failing layer when metric regresses?

  3. Which owner applies the smallest reversible fix?

  4. What validation matrix is required before deployment?

Evidence capsule

diagram
AI-VLSI EVIDENCE CAPSULE 3

PATH: ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/worked-example
WORKLOAD SLICE: <name>
PRIMARY METRIC: <value/trend>
FIRST FAILING LAYER: <data/model/runtime/hardware>
OWNER: <name>
PRIMARY ARTIFACT: <report/profile/dashboard>
DECISION: <ship / rollback / escalate>

Execution drill pack 4

Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/worked-example: metric framing, mechanism proof, hardware implications, and release safety.

Evidence checklist

  • Metric context includes workload, dataset slice, and revision tags.

  • Mechanism explanation links model behavior to observed outcome.

  • Hardware/runtime feasibility is profiled, not assumed.

  • Owner and rollback path are documented before rollout.

Review prompts

  1. Which decision will this model output influence?

  2. What is the first failing layer when metric regresses?

  3. Which owner applies the smallest reversible fix?

  4. What validation matrix is required before deployment?

Evidence capsule

diagram
AI-VLSI EVIDENCE CAPSULE 4

PATH: ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/worked-example
WORKLOAD SLICE: <name>
PRIMARY METRIC: <value/trend>
FIRST FAILING LAYER: <data/model/runtime/hardware>
OWNER: <name>
PRIMARY ARTIFACT: <report/profile/dashboard>
DECISION: <ship / rollback / escalate>

Execution drill pack 5

Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/worked-example: metric framing, mechanism proof, hardware implications, and release safety.

Evidence checklist

  • Metric context includes workload, dataset slice, and revision tags.

  • Mechanism explanation links model behavior to observed outcome.

  • Hardware/runtime feasibility is profiled, not assumed.

  • Owner and rollback path are documented before rollout.

Review prompts

  1. Which decision will this model output influence?

  2. What is the first failing layer when metric regresses?

  3. Which owner applies the smallest reversible fix?

  4. What validation matrix is required before deployment?

Evidence capsule

diagram
AI-VLSI EVIDENCE CAPSULE 5

PATH: ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/worked-example
WORKLOAD SLICE: <name>
PRIMARY METRIC: <value/trend>
FIRST FAILING LAYER: <data/model/runtime/hardware>
OWNER: <name>
PRIMARY ARTIFACT: <report/profile/dashboard>
DECISION: <ship / rollback / escalate>

Execution drill pack 6

Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/worked-example: metric framing, mechanism proof, hardware implications, and release safety.

Evidence checklist

  • Metric context includes workload, dataset slice, and revision tags.

  • Mechanism explanation links model behavior to observed outcome.

  • Hardware/runtime feasibility is profiled, not assumed.

  • Owner and rollback path are documented before rollout.

Review prompts

  1. Which decision will this model output influence?

  2. What is the first failing layer when metric regresses?

  3. Which owner applies the smallest reversible fix?

  4. What validation matrix is required before deployment?

Evidence capsule

diagram
AI-VLSI EVIDENCE CAPSULE 6

PATH: ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/worked-example
WORKLOAD SLICE: <name>
PRIMARY METRIC: <value/trend>
FIRST FAILING LAYER: <data/model/runtime/hardware>
OWNER: <name>
PRIMARY ARTIFACT: <report/profile/dashboard>
DECISION: <ship / rollback / escalate>

Execution drill pack 7

Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/worked-example: metric framing, mechanism proof, hardware implications, and release safety.

Evidence checklist

  • Metric context includes workload, dataset slice, and revision tags.

  • Mechanism explanation links model behavior to observed outcome.

  • Hardware/runtime feasibility is profiled, not assumed.

  • Owner and rollback path are documented before rollout.

Review prompts

  1. Which decision will this model output influence?

  2. What is the first failing layer when metric regresses?

  3. Which owner applies the smallest reversible fix?

  4. What validation matrix is required before deployment?

Evidence capsule

diagram
AI-VLSI EVIDENCE CAPSULE 7

PATH: ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/worked-example
WORKLOAD SLICE: <name>
PRIMARY METRIC: <value/trend>
FIRST FAILING LAYER: <data/model/runtime/hardware>
OWNER: <name>
PRIMARY ARTIFACT: <report/profile/dashboard>
DECISION: <ship / rollback / escalate>

Execution drill pack 8

Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/worked-example: metric framing, mechanism proof, hardware implications, and release safety.

Evidence checklist

  • Metric context includes workload, dataset slice, and revision tags.

  • Mechanism explanation links model behavior to observed outcome.

  • Hardware/runtime feasibility is profiled, not assumed.

  • Owner and rollback path are documented before rollout.

Review prompts

  1. Which decision will this model output influence?

  2. What is the first failing layer when metric regresses?

  3. Which owner applies the smallest reversible fix?

  4. What validation matrix is required before deployment?

Evidence capsule

diagram
AI-VLSI EVIDENCE CAPSULE 8

PATH: ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/worked-example
WORKLOAD SLICE: <name>
PRIMARY METRIC: <value/trend>
FIRST FAILING LAYER: <data/model/runtime/hardware>
OWNER: <name>
PRIMARY ARTIFACT: <report/profile/dashboard>
DECISION: <ship / rollback / escalate>

Execution drill pack 9

Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/worked-example: metric framing, mechanism proof, hardware implications, and release safety.

Evidence checklist

  • Metric context includes workload, dataset slice, and revision tags.

  • Mechanism explanation links model behavior to observed outcome.

  • Hardware/runtime feasibility is profiled, not assumed.

  • Owner and rollback path are documented before rollout.

Review prompts

  1. Which decision will this model output influence?

  2. What is the first failing layer when metric regresses?

  3. Which owner applies the smallest reversible fix?

  4. What validation matrix is required before deployment?

Evidence capsule

diagram
AI-VLSI EVIDENCE CAPSULE 9

PATH: ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/worked-example
WORKLOAD SLICE: <name>
PRIMARY METRIC: <value/trend>
FIRST FAILING LAYER: <data/model/runtime/hardware>
OWNER: <name>
PRIMARY ARTIFACT: <report/profile/dashboard>
DECISION: <ship / rollback / escalate>

Execution drill pack 10

Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/worked-example: metric framing, mechanism proof, hardware implications, and release safety.

Evidence checklist

  • Metric context includes workload, dataset slice, and revision tags.

  • Mechanism explanation links model behavior to observed outcome.

  • Hardware/runtime feasibility is profiled, not assumed.

  • Owner and rollback path are documented before rollout.

Review prompts

  1. Which decision will this model output influence?

  2. What is the first failing layer when metric regresses?

  3. Which owner applies the smallest reversible fix?

  4. What validation matrix is required before deployment?

Evidence capsule

diagram
AI-VLSI EVIDENCE CAPSULE 10

PATH: ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/worked-example
WORKLOAD SLICE: <name>
PRIMARY METRIC: <value/trend>
FIRST FAILING LAYER: <data/model/runtime/hardware>
OWNER: <name>
PRIMARY ARTIFACT: <report/profile/dashboard>
DECISION: <ship / rollback / escalate>

Execution drill pack 11

Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/worked-example: metric framing, mechanism proof, hardware implications, and release safety.

Evidence checklist

  • Metric context includes workload, dataset slice, and revision tags.

  • Mechanism explanation links model behavior to observed outcome.

  • Hardware/runtime feasibility is profiled, not assumed.

  • Owner and rollback path are documented before rollout.

Review prompts

  1. Which decision will this model output influence?

  2. What is the first failing layer when metric regresses?

  3. Which owner applies the smallest reversible fix?

  4. What validation matrix is required before deployment?

Evidence capsule

diagram
AI-VLSI EVIDENCE CAPSULE 11

PATH: ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/worked-example
WORKLOAD SLICE: <name>
PRIMARY METRIC: <value/trend>
FIRST FAILING LAYER: <data/model/runtime/hardware>
OWNER: <name>
PRIMARY ARTIFACT: <report/profile/dashboard>
DECISION: <ship / rollback / escalate>

Execution drill pack 12

Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/worked-example: metric framing, mechanism proof, hardware implications, and release safety.

Evidence checklist

  • Metric context includes workload, dataset slice, and revision tags.

  • Mechanism explanation links model behavior to observed outcome.

  • Hardware/runtime feasibility is profiled, not assumed.

  • Owner and rollback path are documented before rollout.

Review prompts

  1. Which decision will this model output influence?

  2. What is the first failing layer when metric regresses?

  3. Which owner applies the smallest reversible fix?

  4. What validation matrix is required before deployment?

Evidence capsule

diagram
AI-VLSI EVIDENCE CAPSULE 12

PATH: ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/worked-example
WORKLOAD SLICE: <name>
PRIMARY METRIC: <value/trend>
FIRST FAILING LAYER: <data/model/runtime/hardware>
OWNER: <name>
PRIMARY ARTIFACT: <report/profile/dashboard>
DECISION: <ship / rollback / escalate>

Execution drill pack 13

Use this pack to rehearse AI-for-VLSI decision making on ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/worked-example: metric framing, mechanism proof, hardware implications, and release safety.

Evidence checklist

  • Metric context includes workload, dataset slice, and revision tags.

  • Mechanism explanation links model behavior to observed outcome.

  • Hardware/runtime feasibility is profiled, not assumed.

  • Owner and rollback path are documented before rollout.

Review prompts

  1. Which decision will this model output influence?

  2. What is the first failing layer when metric regresses?

  3. Which owner applies the smallest reversible fix?

  4. What validation matrix is required before deployment?

Evidence capsule

diagram
AI-VLSI EVIDENCE CAPSULE 13

PATH: ai-vlsi/accelerator-architecture/mac-arrays-and-systolic/worked-example
WORKLOAD SLICE: <name>
PRIMARY METRIC: <value/trend>
FIRST FAILING LAYER: <data/model/runtime/hardware>
OWNER: <name>
PRIMARY ARTIFACT: <report/profile/dashboard>
DECISION: <ship / rollback / escalate>

Principal AI-VLSI review addendum

Systolic and related MAC array organizations maximize reuse and throughput when data movement is orchestrated with regular flow patterns.

Metric: array utilization, stall ratio, and TOPS/mm2 estimate

Practice this lesson