Legal and Illegal PST Transition Checks

What this topic teaches

Legal and Illegal PST Transition Checks converts LPV concepts into staff-level verification decisions. Transition correctness is not only about start and end states; it depends on guards, temporal ordering, and confirmation events on each arc. Verification therefore encodes every legal PST arc with required preconditions (for example quiescent interconnect, save-ack observed, debug override cleared) and postconditions (such as supply good, isolation release, restore complete) while asserting that all non-enumerated arcs remain unreachable. Illegal transition checks must include both direct jumps and multi-step shortcuts created by overlapping requests, because concurrent software writes or interrupt-driven exits can collapse intended two-hop paths into electrically unsafe single-hop behavior. Advanced checkers track arc provenance, so when a violation occurs they identify which guard was bypassed, which handshake timed out, and whether recovery logic masked the violation by forcing a fallback state after corruption was already possible.

Senior-engineer framing question

When Illegal transition escape rate, transition-checker latency to first error, and percentage of legal arcs exercised with pass/fail evidence. regresses, can you isolate first failing low-power boundary, prove it with artifacts, assign owners, and close with rollback-safe validation?

LOW-POWER VERIFICATION FLOW - Legal and Illegal PST Transition Checks

power intent and mode definitions
      |
      v
domain controls and transition sequencing
      |
      v
simulation behavior (isolation, retention, corruption)
      |
      v
assertions and coverage evidence
      |
      v
triage, bounded fix, and signoff closure

Evidence to collect

• Primary metric: Illegal transition escape rate, transition-checker latency to first error, and percentage of legal arcs exercised with pass/fail evidence..

• Primary artifact: Transition-arc checker specification with guard predicates, timeout rules, and illegal-arc diagnostics taxonomy..

• Owners to include: DV assertion owner, power controller RTL lead, firmware sequencing owner, formal verification owner, SoC integration owner.

• One reproducible failing scenario and one stable comparator run.

• One fixed metadata run with branch and configuration tags locked.

Ownership layers

OWNERSHIP LAYERS - Legal and Illegal PST Transition Checks

+----------------------+--------------------------------+--------------------------------+
| Team                 | Primary responsibility         | Closure artifact               |
+----------------------+--------------------------------+--------------------------------+
| DV assertion owner | scenario intent and closure      | review rationale memo          |
| power controller RTL lead | transition and boundary contract | timeline + assertion packet    |
| firmware sequencing owner | regression signoff readiness     | validation matrix + risk note  |
+----------------------+--------------------------------+--------------------------------+

Decision matrix

EVIDENCE MATRIX - Legal and Illegal PST Transition Checks

+-----------------------------+--------------------------------+--------------------------------+---------------------------+
| Evidence                    | Tells you                      | Does not prove                 | Next action               |
+-----------------------------+--------------------------------+--------------------------------+---------------------------+
| transition timeline traces  | first failing LP phase         | complete root-cause ownership  | correlate with intent map |
| UPF-aware assertion logs    | contract violations by phase   | silicon product impact         | map to scenario severity  |
| corruption/X classification | actionable vs noisy failures   | legal transition completeness  | replay key mode corners   |
| save/restore snapshots      | state integrity movement       | isolation correctness          | pair with crossing checks |
| before-after regressions    | mitigation movement quality    | long-tail stability            | run full matrix           |
+-----------------------------+--------------------------------+--------------------------------+---------------------------+

Key takeaways

• Start with transition-boundary classification before broad methodology changes.

• Tie each LPV claim to one proving artifact and one owner action.

• Close with validation matrix and rollback trigger for signoff safety.

Common pitfalls

• Waiving failures before first-failure boundary classification.

• Changing intent, RTL, and checkers in one step and losing causality.

• Declaring closure on local runs without broader replay coverage.

Low-power verification deep dive

Power-state correctness is a protocol contract: legal transitions, robust sequencing, and safe concurrent event handling.

Concept diagram

PST CONTROL LOOP

state request -> legality check -> handshake sequencing -> mode entry -> monitored exit

Metric graph

STATE RISK MIX

illegal transitions     ██████
sequence race bugs      █████
stable mode paths       ████████

Metrics and artifacts to collect

• PST legality matrix

• illegal transition histogram

• entry/exit handshake coverage

• mode sequencing anomaly log

Mini case study

A sporadic low-power failure closed only after proving a wake-versus-thermal race in PMU transition sequencing.

Debug branches

• Validate legal state graph first.

• Stress concurrent control events and asynchronous wakeups.

• Bind fixes to explicit transition and owner contracts.

Senior review question

Ask: what exact low-power transition boundary failed first, and which artifact proves the closure claim reproducibly?

Key takeaways

• Tie each LPV claim to a concrete transition boundary and one proving artifact.

• Prefer minimal reversible fixes with explicit owner and rollback criteria.

Common pitfalls

• Treating power-aware failures as random before boundary classification.

• Waiving X-prop failures before proving impact and root cause.

• Declaring closure without deterministic replay across key modes.