Low Power Verification · All levels

Legal and Illegal PST Transition Checks: Debug Playbook

Debug Playbook for Legal and Illegal PST Transition Checks.

Debug playbook

Debug Playbook for Legal and Illegal PST Transition Checks is anchored on Illegal transition escape rate, transition-checker latency to first error, and percentage of legal arcs exercised with pass/fail evidence.. Convert observations into mechanism-backed and owner-bound actions.

Freeze seed, metadata, and boundary under investigation.
Locate first persistent low-power phase divergence.
Classify mechanism: setup, transition, boundary, retention, or X-prop class.
Apply one focused reproducer and one bounded fix.
Re-run determinism and broader regression matrix.

Review memo template

diagram

LPV REVIEW MEMO - Power State Verification / Legal and Illegal PST Transition Checks

1. Symptom
   - Failing metric: Illegal transition escape rate, transition-checker latency to first error, and percentage of legal arcs exercised with pass/fail evidence.
   - Trigger context: <seed/mode/sequence>
   - First failing phase: <entry/off/exit/boundary>

2. Mechanism hypothesis
   - Candidate mechanism: Transition correctness is not only about start and end states; it depends on guards, temporal ordering, and confirmation events on each arc. Verification therefore encodes every legal PST arc with required preconditions (for example quiescent interconnect, save-ack observed, debug override cleared) and postconditions (such as supply good, isolation release, restore complete) while asserting that all non-enumerated arcs remain unreachable. Illegal transition checks must include both direct jumps and multi-step shortcuts created by overlapping requests, because concurrent software writes or interrupt-driven exits can collapse intended two-hop paths into electrically unsafe single-hop behavior. Advanced checkers track arc provenance, so when a violation occurs they identify which guard was bypassed, which handshake timed out, and whether recovery logic masked the violation by forcing a fallback state after corruption was already possible.
   - Competing hypotheses: setup, transition race, boundary bug, retention drift, X-prop noise
   - Missing evidence: <trace/assertion/report>

3. Proposed action
   - Smallest reversible change: <intent/RTL/checker/flow>
   - Expected movement: <failure trend/replay stability>
   - Regression risk: compatibility, coverage, signoff delay

4. Signoff
   - Required artifact: Transition-arc checker specification with guard predicates, timeout rules, and illegal-arc diagnostics taxonomy.
   - Required owners: DV assertion owner, power controller RTL lead, firmware sequencing owner, formal verification owner, SoC integration owner
   - Final decision: ship, bounded rollout, rollback, or escalate

Low-power verification deep dive

Power-state correctness is a protocol contract: legal transitions, robust sequencing, and safe concurrent event handling.

Concept diagram

diagram

PST CONTROL LOOP

state request -> legality check -> handshake sequencing -> mode entry -> monitored exit

Metric graph

diagram

STATE RISK MIX

illegal transitions     ██████
sequence race bugs      █████
stable mode paths       ████████

Metrics and artifacts to collect

PST legality matrix
illegal transition histogram
entry/exit handshake coverage
mode sequencing anomaly log

Mini case study

A sporadic low-power failure closed only after proving a wake-versus-thermal race in PMU transition sequencing.

Debug branches

Validate legal state graph first.
Stress concurrent control events and asynchronous wakeups.
Bind fixes to explicit transition and owner contracts.

Senior review question

Ask: what exact low-power transition boundary failed first, and which artifact proves the closure claim reproducibly?

Key takeaways

Tie each LPV claim to a concrete transition boundary and one proving artifact.
Prefer minimal reversible fixes with explicit owner and rollback criteria.

Common pitfalls

Treating power-aware failures as random before boundary classification.
Waiving X-prop failures before proving impact and root cause.
Declaring closure without deterministic replay across key modes.

Debug ladder

Sequence: reproduce -> classify -> isolate boundary -> prove mechanism -> bounded fix.

Avoid mixed fixes before first-principles classification.

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