Answer each question out loud before opening it. If you miss more than three in the checkpoint, revisit the lessons linked at the end.
The two writes took paths that could reorder and nothing forced order; fix with one ordered path, a shared ID, a final acknowledgement, or a fence.
None; and none between the read and write channels.
At the point of serialisation: where competing requests first pass through one in-order structure.
Only if the response came from the destination; a bufferable write may be acknowledged early by a buffer.
It holds later accesses until earlier ones have completed to the promised point; every buffer on the path must drain or keep order.
Producer/consumer: a read-back must confirm earlier writes have landed.
An MSI is a posted write that may not pass the device's earlier posted writes; a wire takes a separate path.
Only a load passing an earlier store to a different address (store buffering).
Task. A NIC behind a PCIe-to-AXI bridge writes received packets into memory, then a completion entry, then an MSI. The bridge has four AXI write paths. Make the whole chain correct and fast.
On PCIe: the NIC marks packet-data writes Relaxed Ordering (if the platform enables it) and leaves the completion entry and the MSI strictly ordered. In the bridge: spread relaxed data writes across the four AXI IDs for throughput; keep strict writes ordered after every earlier write, either on one ID that the data writes also drain through, or by holding the completion entry until all earlier writes' responses have returned from the destination (non-bufferable, or an end-to-end acknowledgement). The MSI is held behind the completion entry the same way. In the driver: the handler reads the completion entry, checks its valid bit or sequence number, then reads the data. Verify with heavy inbound traffic and assert, in simulation, that no MSI or completion entry reaches its target before every earlier data write.
A producer writes a payload, then a separate location announcing it; the consumer waits for the announcement, then reads the payload.
Same ID, same address, same source to same destination, global.
Each target serialises its own requests; nothing orders one target's against another's.
That it will be performed, and that later writes in its ordering domain (as the specification defines it, not simply "the same path") will not overtake it.
A stall until earlier accesses complete, and lost overlap across the fence.
Producer/consumer correctness and deadlock avoidance.
Independent bulk data, never the flag that announces it.
Forwarding or blocking on an address match, address-based routing, or waiting for the write's final acknowledgement.
Message passing seeing the flag but stale data: forbidden under TSO, allowed on weak models without barriers.
Add relaxation the source did not ask for (spread strict writes across IDs, mark traffic relaxed).