Read across for one system; read down to see how differently the same ordering questions are answered.
AXI | PCI Express | x86 (TSO) | Arm / RISC-V (weak) | DCLink | |
|---|---|---|---|---|---|
Scope of order | Same ID, per channel | Per path, per traffic class, by transaction type | Per core: stores in order; loads may pass stores | None without barriers or dependencies | None between tags |
Read vs earlier write | No order across channels; wait for the write response | A read may not pass earlier posted writes | A load may pass an earlier store (different address) | May reorder | Wait for CPL or FENCE |
Relaxation | Use different IDs | Relaxed Ordering bit, ID-Based Ordering | — | The default | — |
Fence | None: wait for responses | None: a read-back flushes posted writes | MFENCE, SFENCE, LFENCE | Arm DMB/DSB; RISC-V FENCE; acquire/release | FENCE request (step 6) |
What a write response means | Bufferable: accepted; non-bufferable: at destination | Memory writes get no response | — | — | Performed |
Interrupt ordering | Wires: separate path | MSI is a posted write behind the data | — | — | — |
Every system orders within a scope, never globally, and leaves the rest to fences, waits or rules.
Producer/consumer is the common need: PCIe builds it into its passing rules; AXI leaves it to IDs and responses; processors use barriers or release/acquire.
Bridges sit between different vocabularies and must translate each guarantee explicitly (lesson 7.11).