Answer each question out loud before opening it. If you miss more than three in the checkpoint, revisit the lessons linked at the end.
Private caches hold copies that go stale when another core writes; coherence enforces single-writer, multiple-reader and the latest-value rule per location.
Writes come in runs; invalidation pays once per run, update pays per write.
Knowledge that the copy is the only one, so the first write is silent; it halves bus traffic for private data.
Dirty data can be shared without writing it back; the owner supplies it.
When broadcast traffic and lookups to many caches dominate; directories message only holders.
Requester to home, home forwards to owner, owner sends data to requester.
No: coherence orders one location; the memory model governs cross-location order.
I/O coherence in hardware, or clean before device reads and invalidate around device writes, with barriers and line-aligned buffers.
Task. A 32-core chip in 8 clusters of 4 shares a last-level cache. Design how coherence is maintained within and between clusters, how a dirty miss to another cluster is served, and how a non-caching DMA engine and a caching accelerator attach.
Within a cluster: snooping among 4 caches (cheap broadcast) with MESI or MOESI. Between clusters: a directory or snoop filter at the shared cache's home slices, tracking which clusters hold each line, so requests snoop only those clusters. Home slices order requests per address. A dirty miss to another cluster: requester to home slice, home forwards to the owning cluster, the owner sends data directly to the requester (three hops), and updates the home; O or Shared Dirty states avoid writebacks for dirty sharing. Size the snoop filter for the combined cache capacity with margin to avoid back-invalidation thrash. DMA engine: I/O coherent (ACE-Lite-style) requests to the home, which snoops holders: reads get dirty data, writes invalidate. Accelerator with a cache: a fully coherent agent tracked by the directory like a cluster. Define race rules for writebacks crossing forwards, and verify SWMR with a model checker on the protocol tables.
At any time a location has one writer or any number of readers, never both.
Independent variables in one line make it bounce between caches on every write.
Invalidate 1 + 2 = 3; update 10.
M (already) and E (becomes M).
Designates one clean sharer to answer requests.
The line's home node.
Evicting a directory or snoop-filter entry forces caches holding that line to invalidate it.
Memory.
Yes.
The CPU may have speculatively refetched lines during the DMA.