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Course contents

  • How to Use This Course
  • Reading Paths
  • Concept Map
  • How to Read the Diagrams
  • Part 0: What Is a Protocol?10
  • Part 1: Timing and Clocking11
  • Part 2: Encoding and Framing12
  • Part 3: Handshakes13
  • Part 4: Flow Control17
  • Part 5: Transactions19
  • Part 6: Concurrency and Performance17
  • Part 7: Ordering13
  • Part 8: Sharing and Arbitration12
  • Part 9: Deadlock and Liveness13
  • Part 10: Reliability and Recovery20
  • Part 11: Bring-Up and Link Management10
  • Part 12: Power8
  • Part 13: Shared State and Coherence9
    • Why Coherence
    • Invalidate or Update
    • MSI, MESI and MOESI
    • Snooping or Directory
    • Ownership and Forwarding
    • Coherence and Consistency
    • I/O Coherence and Cache Maintenance
    • Protocols Compared: Shared State and Coherence
    • Drills: Shared State and Coherence
  • Part 14: Security and Isolation7
  • Part 15: Specifying and Verifying11
  • Part 16: Protocols Dissected17
  • Part 17: Capstones5
  • Part 18: Interview Preparation6
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‹Part 13: Shared State and Coherence
  1. Topics
  2. First Principles of Hardware Protocols
  3. Part 13: Shared State and Coherence
  4. Ownership and Forwarding

Part 13 · Shared State and Coherence · Senior (S)

Ownership and Forwarding

Every line needs one agent responsible for answering requests and for its dirty data: memory or a cache. How ownership moves, how a request is forwarded to the owner, and why the number of hops on that path sets the latency of a shared miss.

On this page

    Note

    Level: Senior (S) · Answers: What if there are several copies of one value?

    Before this: Snooping or Directory

    Core 3 misses on a line. The latest value is not in memory: core 12 wrote it a moment ago and holds it Modified. Core 3's request goes to the line's home, which looks it up, sees core 12 owns it, and sends the request on. Core 12 sends the data to core 3. Three messages in sequence, each crossing the chip. On a large chip, this path, not memory, is often the slowest way to get data.

    Who is responsible for each line, and how does a request reach them?

    The obvious answer, and why it breaks

    The obvious answer is that memory is responsible: requests go to memory and memory answers. That fails as soon as a cache holds the line dirty: memory's copy is stale, and answering from it breaks the data-value rule (lesson 13.1). Some agent must always know it holds the latest data and must answer for it. That agent is the owner, and it can be memory or any cache.

    The idea: one owner per line, and forwarding to it

    • Exactly one owner per line at a time: the agent that supplies data on a request and is responsible for eventually writing dirty data back.

    • Memory owns lines that no cache holds dirty (in protocols with F, a designated clean sharer may answer instead).

    • A cache owns a line it holds in M (or O in MOESI): it must answer for it.

    • Ownership moves with writes and with requests: a write makes the writer the owner; a read of an M line either moves ownership back to memory (writeback, M to S) or keeps it in the cache (M to O).

    • Forwarding: in a directory protocol, the home sends a request on to the owner, which replies directly to the requester.

    Three messages in sequence: request to the home, forward to the owner, data straight to the requester; the home's records are updated off the critical path.

    Hops set the latency

    Path

    Hops on the critical path

    When

    Memory owns it

    2: requester to home, home (with memory) to requester

    Line not dirty in any cache

    Forward to owner

    3: requester to home, home to owner, owner to requester

    Line dirty in another cache

    Snoop broadcast

    2: requester to all, owner to requester

    Small snooping systems

    Four-hop (no direct reply)

    4: owner replies to the home, home replies to requester

    Simpler protocols; slower

    Protocols work hard to keep shared misses at two or three hops: direct owner-to-requester replies, forwarding states (O, F) so a cache rather than distant memory can answer, and placing homes near their likely users.

    How real protocols chose

    Protocol

    Ownership and forwarding

    MOESI

    Owned: a cache keeps ownership of dirty shared data and answers requests for it (fact T23)

    MESIF

    Forward: one clean sharer is designated to answer, so memory need not and other sharers stay quiet (fact T23)

    AMBA CHI

    The home node receives requests and can have the snooped owner send data directly to the requester (fact A23)

    What breaks

    A protocol design (illustrative) let an owner evict a dirty line (sending a writeback to the home) at the same moment the home forwarded it a request. The forward found no line; the owner, having given up ownership, ignored it, and the requester waited for ever. The fix was a defined race rule: the owner keeps the data until its writeback is acknowledged and answers any forward that arrives meanwhile. Races between writebacks and forwards are a classic source of coherence deadlocks.

    Why this matters

    Senior lens. Track, for every line, exactly one owner, and check that every message that moves ownership (writes, forwards, writebacks, evictions) keeps it unique even when two of them cross. Most coherence protocol bugs are races between ownership changes, and the latency of shared data is set by how many hops it takes to reach the owner.

    Interview

    Asked: "What is a three-hop miss?"

    Weak answer: A miss that takes three cycles.

    Strong answer: A miss in a directory protocol where the data is dirty in another cache: the request goes to the line's home (hop one), the home forwards it to the owning cache (hop two), and the owner sends the data directly to the requester (hop three), updating the home off the critical path. It's slower than a two-hop miss served by memory at the home, so protocols add owner and forward states so a nearby cache can answer, and allow direct owner-to-requester replies instead of routing data back through the home.

    Follow-ups: (1) What happens if the owner is evicting the line as the forward arrives? (2) What does the O state change about ownership?

    Check yourself Who owns a line that is Shared in three caches and clean, under MESI?

    Memory: no cache holds it dirty, so memory supplies it (unless a protocol designates a forwarder, as MESIF's F state does).

    Check yourself Why should the owner reply directly to the requester rather than through the home?

    It removes a hop from the critical path: three hops instead of four.

    Key takeaways

    • Every line has exactly one owner, memory or a cache, which supplies data and is responsible for dirty data.

    • Directory protocols forward requests to the owner, which replies directly: a three-hop miss.

    • Ownership races (writeback against forward) must have defined rules; hops set shared-miss latency.

    Keep going

    Next: Lesson 13.6, Coherence and Consistency. Coherence orders one address; consistency orders all of them.

    Related topics

    • Part 13 overview: Shared State and Coherence

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    See also

    • Why Coherence
    • Invalidate or Update
    • MSI, MESI and MOESI