Use these drills after completing all topics in Clock & Reset Architecture. Answer with baseline, boundary, owner, metric, artifact, and regression scope.
[INT][SOC][CLOCK-RESET-ARCHITECTURE]
Q: What is the first check in a reset-related boot hang?
A:
Validate dependency order: power-good, PLL lock, clock enable, then reset release per domain.
FOLLOW-UP TRAP: Jumping straight to firmware timeout tuning.[INT][SOC][CLOCK-RESET-ARCHITECTURE]
Q: Why can test mode break a healthy functional reset strategy?
A:
Clock/reset muxing and constraints differ in scan/test modes, so functional assumptions may not hold under ATPG sequencing.
FOLLOW-UP TRAP: Assuming one reset sequence fits all modes.[INT][SOC][CLOCK-RESET-ARCHITECTURE]
Q: How do you explain clock architecture ownership in one line?
A:
Architecture defines domains and intent; CTS/STA own implementation and proof across modes/corners.
FOLLOW-UP TRAP: Treating clocking as only a PD task.BASELINE -> OWNER -> CONTRACT -> METRIC -> FIX -> REGRESSIONCLOCK/RESET FLOW
pll lock -> clock enable -> reset release -> domain readyState baseline manifest and owner with every closure metric.
Run cross-domain regression after every top-level fix.
Comparing results across different manifests.
Unowned issues slipping through review cycles.
Waiving risks without expiry and validation plan.