Clock/Reset + DFT Interactions

What this topic teaches

Clock/Reset + DFT Interactions is about making top-level contracts measurable and enforceable. Functional and test clocks/resets share infrastructure; missing mode-specific constraints and mux assumptions often break ATPG or silicon bring-up. The hard part is proving owner accountability and reproducibility under schedule pressure.

The senior-engineer question

When scan mode timing escapes, test-mode bring-up issues moves, can you identify the first broken boundary, responsible owner, and smallest reversible fix with complete regression scope?

SOC INTEGRATION STACK — Clock/Reset + DFT Interactions

program contract (scope, milestones, ownership)
        |
        v
architecture contract (budgets, interfaces, assumptions)
        |
        v
implementation contract (rtl, timing, physical, package)
        |
        v
validation contract (bring-up, workload, signoff evidence)
        |
        v
release contract (manifest, waivers, tapeout decision)

Debug rule: always identify which contract layer broke first.

Picture the integration flow

Start by drawing boundaries and ownership before diving into logs. The diagrams below are the whiteboard models to reproduce in reviews.

Functional vs test modes

MODE MATRIX

mode         clock source      reset rule
func         pll/main          staged release
scan_shift   test_clk          scan_reset gated
scan_capture test_clk_fast     atpg capture window

Integration sequence

SOC INTEGRATION FLOW — Clock/Reset + DFT Interactions

requirements + budgets
        |
        v
IP handoff + collateral check
        |
        v
integration build + bring-up smoke
        |
        v
cross-domain signoff evidence
        |
        v
tapeout readiness decision

Metric in focus: scan mode timing escapes, test-mode bring-up issues

Layer ownership

SOC INTEGRATION LAYERS — Clock/Reset + DFT Interactions

layer               owns                          failure mode
-----------------   ---------------------------   ------------------------
architecture        partition + contracts         impossible budgets
ip handoff          models + collateral           integration mismatch
fabric/clock/reset  global behavior               domain deadlock
physical/package    route + SI/PI + IO            late closure churn
signoff process     manifests + waivers           non-reproducible claims
program governance  owners + escalations          schedule collapse

Evidence to collect

• Primary metric: scan mode timing escapes, test-mode bring-up issues.

• Primary artifact: mode matrix, scan clock/reset constraints, DFT integration checklist.

• Owners to include: DFT lead, STA lead, clock/reset owners.

• Manifest baseline and revision for every claim.

• One focused repro and one full-system regression result.

Ownership map

OWNERSHIP MAP — Clock/Reset + DFT Interactions

artifact             owner
-----------------    -----------------
primary owner     DFT lead
co-owner          STA lead
review owner      clock/reset owners

No top-level issue should remain ownerless beyond one review cycle.

Subpages in this topic

Each topic includes 15 subpages: mechanism, inputs/outputs, reports, debug, worked example, pitfalls, interview, checklist, theory, design space, expanded case study, walkthrough, comparison matrix, software view, and silicon PPA impact.

Key takeaways

• Tie every integration claim to a baseline manifest and owner.

• Fix the first broken boundary before broad optimizations.

• Regression scope is part of the fix, not a follow-up task.

Common pitfalls

• Comparing results across changing baselines.

• Unowned risks hidden behind green aggregate metrics.

• Waiving high-impact issues without expiry and revalidation.

SoC deep dive

Clock/reset assumptions must be globally consistent across functional and test modes.

Concept diagram

CLOCK/RESET FLOW
pll lock -> clock enable -> reset release -> domain ready

Metric graph

BOOT STABILITY
stable boots ████████
reset hangs  ███

Reports and artifacts

• clock architecture report

• reset release timing

• mode matrix

• boot trace summary

Mini case study

Intermittent boot hang traced to one domain releasing reset before dependent clock was stable.

Debug branches

• Check mode-specific constraints

• Trace reset dependencies

• Correlate firmware sequencing

Senior review question

Ask: what baseline, owner, and artifact prove this topic is truly closed?

Key takeaways

• State baseline manifest and owner with every closure metric.

• Run cross-domain regression after every top-level fix.

Common pitfalls

• Comparing results across different manifests.

• Unowned issues slipping through review cycles.

• Waiving risks without expiry and validation plan.