Interview drills

Interview Drills for Clock/Reset + DFT Interactions focuses on scan mode timing escapes, test-mode bring-up issues. The goal is to map symptoms to boundary contracts, owner actions, and regression-proof closure.

PROMPT
You observe scan mode timing escapes, test-mode bring-up issues in Clock/Reset + DFT Interactions. Explain root cause and closure plan.

STRONG ANSWER
1. Names baseline manifest and failing boundary.
2. Explains Functional and test clocks/resets share infrastructure; missing mode-specific constraints and mux assumptions often break ATPG or silicon bring-up.
3. Requests mode matrix, scan clock/reset constraints, DFT integration checklist.
4. Proposes minimal reversible fix + full regression scope.

WEAK ANSWER
Suggests broad optimizations or owner blame without baseline and artifact evidence.

Diagram to draw on whiteboard

Functional vs test modes

MODE MATRIX

mode         clock source      reset rule
func         pll/main          staged release
scan_shift   test_clk          scan_reset gated
scan_capture test_clk_fast     atpg capture window

Root-cause tree to narrate

ROOT-CAUSE TREE — Clock/Reset + DFT Interactions

scan mode timing escapes, test-mode bring-up issues regressed
         |
   same baseline manifest?
      /           \
    no             yes
    |               |
version/collateral  real integration
mismatch            contract break
 /       \            |
inputs    env      isolate domain
drift     drift    and first failure

SoC deep dive

Clock/reset assumptions must be globally consistent across functional and test modes.

Concept diagram

CLOCK/RESET FLOW
pll lock -> clock enable -> reset release -> domain ready

Metric graph

BOOT STABILITY
stable boots ████████
reset hangs  ███

Reports and artifacts

• clock architecture report

• reset release timing

• mode matrix

• boot trace summary

Mini case study

Intermittent boot hang traced to one domain releasing reset before dependent clock was stable.

Debug branches

• Check mode-specific constraints

• Trace reset dependencies

• Correlate firmware sequencing

Senior review question

Ask: what baseline, owner, and artifact prove this topic is truly closed?

Key takeaways

• State baseline manifest and owner with every closure metric.

• Run cross-domain regression after every top-level fix.

Common pitfalls

• Comparing results across different manifests.

• Unowned issues slipping through review cycles.

• Waiving risks without expiry and validation plan.

Principal SoC review addendum

Functional and test clocks/resets share infrastructure; missing mode-specific constraints and mux assumptions often break ATPG or silicon bring-up.

Metric: scan mode timing escapes, test-mode bring-up issues