Worked example

Worked Example for Clock/Reset + DFT Interactions focuses on scan mode timing escapes, test-mode bring-up issues. The goal is to map symptoms to boundary contracts, owner actions, and regression-proof closure.

A review detects scan mode timing escapes, test-mode bring-up issues. Strong analysis starts by freezing baseline and proving where the first boundary failed in Clock/Reset + DFT Interactions.

Sequence under inspection

SOC INTEGRATION FLOW — Clock/Reset + DFT Interactions

requirements + budgets
        |
        v
IP handoff + collateral check
        |
        v
integration build + bring-up smoke
        |
        v
cross-domain signoff evidence
        |
        v
tapeout readiness decision

Metric in focus: scan mode timing escapes, test-mode bring-up issues

Functional vs test modes

MODE MATRIX

mode         clock source      reset rule
func         pll/main          staged release
scan_shift   test_clk          scan_reset gated
scan_capture test_clk_fast     atpg capture window

1. Capture failing artifact and manifest tags.

2. Map failure to one owner boundary.

3. Verify mechanism using one reduced repro.

4. Compare against mode matrix, scan clock/reset constraints, DFT integration checklist.

5. Select one reversible fix and define full regression upfront.

Did the fix work?

BEFORE / AFTER FIX — Clock/Reset + DFT Interactions

risk index
 0 |                    --- target
40 |    ● regression
65 |         ● before fix
20 |              ● after fix
    +-------------------------------> iteration
Always verify collateral, regression suite, and owner signoff.

SoC deep dive

Clock/reset assumptions must be globally consistent across functional and test modes.

Concept diagram

CLOCK/RESET FLOW
pll lock -> clock enable -> reset release -> domain ready

Metric graph

BOOT STABILITY
stable boots ████████
reset hangs  ███

Reports and artifacts

• clock architecture report

• reset release timing

• mode matrix

• boot trace summary

Mini case study

Intermittent boot hang traced to one domain releasing reset before dependent clock was stable.

Debug branches

• Check mode-specific constraints

• Trace reset dependencies

• Correlate firmware sequencing

Senior review question

Ask: what baseline, owner, and artifact prove this topic is truly closed?

Key takeaways

• State baseline manifest and owner with every closure metric.

• Run cross-domain regression after every top-level fix.

Common pitfalls

• Comparing results across different manifests.

• Unowned issues slipping through review cycles.

• Waiving risks without expiry and validation plan.

Principal SoC review addendum

Functional and test clocks/resets share infrastructure; missing mode-specific constraints and mux assumptions often break ATPG or silicon bring-up.

Metric: scan mode timing escapes, test-mode bring-up issues