Inputs and outputs contract

Inputs & Outputs for Clock/Reset + DFT Interactions focuses on scan mode timing escapes, test-mode bring-up issues. The goal is to map symptoms to boundary contracts, owner actions, and regression-proof closure.

Treat these as a signed integration contract. Ambiguity here causes multi-team debug loops where everyone is right inside their own assumptions.

INPUTS
  - baseline manifest (versions + hashes)
  - interface/budget contract revision
  - mode assumptions (functional/test/low-power)
  - owner accountability map

OUTPUTS
  - measurable closure deltas
  - owner-approved fix proposal
  - regression evidence package
  - risk/waiver disposition

Integration sequence

SOC INTEGRATION FLOW — Clock/Reset + DFT Interactions

requirements + budgets
        |
        v
IP handoff + collateral check
        |
        v
integration build + bring-up smoke
        |
        v
cross-domain signoff evidence
        |
        v
tapeout readiness decision

Metric in focus: scan mode timing escapes, test-mode bring-up issues

Ownership map

OWNERSHIP MAP — Clock/Reset + DFT Interactions

artifact             owner
-----------------    -----------------
primary owner     DFT lead
co-owner          STA lead
review owner      clock/reset owners

No top-level issue should remain ownerless beyond one review cycle.

SoC deep dive

Clock/reset assumptions must be globally consistent across functional and test modes.

Concept diagram

CLOCK/RESET FLOW
pll lock -> clock enable -> reset release -> domain ready

Metric graph

BOOT STABILITY
stable boots ████████
reset hangs  ███

Reports and artifacts

• clock architecture report

• reset release timing

• mode matrix

• boot trace summary

Mini case study

Intermittent boot hang traced to one domain releasing reset before dependent clock was stable.

Debug branches

• Check mode-specific constraints

• Trace reset dependencies

• Correlate firmware sequencing

Senior review question

Ask: what baseline, owner, and artifact prove this topic is truly closed?

Key takeaways

• State baseline manifest and owner with every closure metric.

• Run cross-domain regression after every top-level fix.

Common pitfalls

• Comparing results across different manifests.

• Unowned issues slipping through review cycles.

• Waiving risks without expiry and validation plan.

Principal SoC review addendum

Functional and test clocks/resets share infrastructure; missing mode-specific constraints and mux assumptions often break ATPG or silicon bring-up.

Metric: scan mode timing escapes, test-mode bring-up issues