Clock/Reset + DFT Interactions: Debug Playbook

Debug playbook

Debug Playbook for Clock/Reset + DFT Interactions focuses on scan mode timing escapes, test-mode bring-up issues. The goal is to map symptoms to boundary contracts, owner actions, and regression-proof closure.

Integration debug is a search for the first contract break, not the loudest downstream failure signature.

Root-cause tree

ROOT-CAUSE TREE — Clock/Reset + DFT Interactions

scan mode timing escapes, test-mode bring-up issues regressed
         |
   same baseline manifest?
      /           \
    no             yes
    |               |
version/collateral  real integration
mismatch            contract break
 /       \            |
inputs    env      isolate domain
drift     drift    and first failure

1. Freeze baseline manifest and owner matrix.

2. Find first failing boundary and earliest reproducible symptom.

3. Classify failure type: contract, collateral, implementation, or governance.

4. Prove with one reduced experiment.

5. Apply smallest owner-controlled fix.

6. Run focused verification and full cross-domain regression.

Review memo template

STAFF SOC REVIEW MEMO — Clock & Reset Architecture / Clock/Reset + DFT Interactions

1. Symptom
   - Watched metric: scan mode timing escapes, test-mode bring-up issues
   - Failing integration boundary: <domain/interface>
   - Baseline manifest: <hash/tag>
   - Repro setup: <sim/emulation/fpga/silicon + fw tag>

2. Mechanism hypothesis
   - Primary mechanism: Functional and test clocks/resets share infrastructure; missing mode-specific constraints and mux assumptions often break ATPG or silicon bring-up.
   - Competing hypothesis: <contract drift, collateral mismatch, implementation bug, governance gap>
   - Missing evidence: <trace, report, checklist, signoff artifact>

3. Proposed action
   - Minimal reversible fix: <contract update, config patch, RTL fix, process guardrail>
   - Expected metric movement: <delta and scope>
   - Regression risk: timing, power, functionality, schedule

4. Signoff
   - Re-run artifact: mode matrix, scan clock/reset constraints, DFT integration checklist
   - Required owners: DFT lead, STA lead, clock/reset owners
   - Final decision: close, waive (bounded), or escalate

SoC deep dive

Clock/reset assumptions must be globally consistent across functional and test modes.

Concept diagram

CLOCK/RESET FLOW
pll lock -> clock enable -> reset release -> domain ready

Metric graph

BOOT STABILITY
stable boots ████████
reset hangs  ███

Reports and artifacts

• clock architecture report

• reset release timing

• mode matrix

• boot trace summary

Mini case study

Intermittent boot hang traced to one domain releasing reset before dependent clock was stable.

Debug branches

• Check mode-specific constraints

• Trace reset dependencies

• Correlate firmware sequencing

Senior review question

Ask: what baseline, owner, and artifact prove this topic is truly closed?

Key takeaways

• State baseline manifest and owner with every closure metric.

• Run cross-domain regression after every top-level fix.

Common pitfalls

• Comparing results across different manifests.

• Unowned issues slipping through review cycles.

• Waiving risks without expiry and validation plan.

Principal SoC review addendum

Functional and test clocks/resets share infrastructure; missing mode-specific constraints and mux assumptions often break ATPG or silicon bring-up.

Metric: scan mode timing escapes, test-mode bring-up issues