Step-by-step analysis walkthrough

Use when you own Clock/Reset + DFT Interactions in a top-level integration review.

1. Open latest integration baseline and manifest.

2. Inspect failing metric by domain.

3. Trace first failing contract boundary.

4. Collect artifacts and assign single-thread owner.

5. Define minimal proof experiment.

6. Apply smallest reversible fix.

7. Run focused check then full regression.

8. Update dashboard and governance log.

9. Decide: close, waive with expiry, or escalate.

10. Publish final review memo.

Artifacts to collect

• mode matrix, scan clock/reset constraints, DFT integration checklist

• baseline manifest

• owner matrix

• regression summary

• risk memo

Decision memo template

SOC DECISION MEMO — Clock/Reset + DFT Interactions
baseline:
metric:
root cause:
fix:
residual risk:
owners: DFT lead, STA lead, clock/reset owners

Reference visuals

Functional vs test modes

MODE MATRIX

mode         clock source      reset rule
func         pll/main          staged release
scan_shift   test_clk          scan_reset gated
scan_capture test_clk_fast     atpg capture window

SoC deep dive

Clock/reset assumptions must be globally consistent across functional and test modes.

Concept diagram

CLOCK/RESET FLOW
pll lock -> clock enable -> reset release -> domain ready

Metric graph

BOOT STABILITY
stable boots ████████
reset hangs  ███

Reports and artifacts

• clock architecture report

• reset release timing

• mode matrix

• boot trace summary

Mini case study

Intermittent boot hang traced to one domain releasing reset before dependent clock was stable.

Debug branches

• Check mode-specific constraints

• Trace reset dependencies

• Correlate firmware sequencing

Senior review question

Ask: what baseline, owner, and artifact prove this topic is truly closed?

Key takeaways

• State baseline manifest and owner with every closure metric.

• Run cross-domain regression after every top-level fix.

Common pitfalls

• Comparing results across different manifests.

• Unowned issues slipping through review cycles.

• Waiving risks without expiry and validation plan.

Principal SoC review addendum

Functional and test clocks/resets share infrastructure; missing mode-specific constraints and mux assumptions often break ATPG or silicon bring-up.

Metric: scan mode timing escapes, test-mode bring-up issues