Silicon PPA and closure impact

Skew, reset timing, and mode transitions dominate bring-up escapes.

Area drivers

• Guardband margins

• late ECO spillover

Power drivers

• Emergency frequency guards

• clocking overhead

Timing impact

• Cross-domain path regressions

• late closure churn

PD consequences

• Route congestion from top-level fixes

• package-driven detours

Verification burden

• Re-validation of waived assumptions

PPA RISK — Clock/Reset + DFT Interactions
area/power/timing confidence vs integration velocity

PPA takeaways

• Integration discipline reduces expensive late-stage silicon risk.

Design option PPA snapshot

BEFORE / AFTER FIX — Clock/Reset + DFT Interactions

risk index
 0 |                    --- target
40 |    ● regression
65 |         ● before fix
20 |              ● after fix
    +-------------------------------> iteration
Always verify collateral, regression suite, and owner signoff.

SoC deep dive

Clock/reset assumptions must be globally consistent across functional and test modes.

Concept diagram

CLOCK/RESET FLOW
pll lock -> clock enable -> reset release -> domain ready

Metric graph

BOOT STABILITY
stable boots ████████
reset hangs  ███

Reports and artifacts

• clock architecture report

• reset release timing

• mode matrix

• boot trace summary

Mini case study

Intermittent boot hang traced to one domain releasing reset before dependent clock was stable.

Debug branches

• Check mode-specific constraints

• Trace reset dependencies

• Correlate firmware sequencing

Senior review question

Ask: what baseline, owner, and artifact prove this topic is truly closed?

Key takeaways

• State baseline manifest and owner with every closure metric.

• Run cross-domain regression after every top-level fix.

Common pitfalls

• Comparing results across different manifests.

• Unowned issues slipping through review cycles.

• Waiving risks without expiry and validation plan.

Principal SoC review addendum

Functional and test clocks/resets share infrastructure; missing mode-specific constraints and mux assumptions often break ATPG or silicon bring-up.

Metric: scan mode timing escapes, test-mode bring-up issues