Use these drills after completing all topics in Memory Maps & I/O. Answer with baseline, boundary, owner, metric, artifact, and regression scope.
[INT][SOC][MEMORY-MAPS-IO]
Q: What is a strong address-map governance rule?
A:
No map change merges without decode conflict checks, software impact assessment, and signed baseline revision.
FOLLOW-UP TRAP: Treating map edits as low-risk register updates.[INT][SOC][MEMORY-MAPS-IO]
Q: Why do interrupt bugs survive pre-silicon tests?
A:
Priority/affinity assumptions differ between synthetic tests and real firmware scheduling behavior.
FOLLOW-UP TRAP: Blaming only driver ISR code.[INT][SOC][MEMORY-MAPS-IO]
Q: What proves HW/SW boot contract health?
A:
A reproducible boot trace showing each stage transition under the declared reset defaults and map revision.
FOLLOW-UP TRAP: Passing one ad-hoc lab boot as signoff evidence.BASELINE -> OWNER -> CONTRACT -> METRIC -> FIX -> REGRESSIONHW/SW CONTRACT
address map + interrupt model + io defaults -> firmware behaviorState baseline manifest and owner with every closure metric.
Run cross-domain regression after every top-level fix.
Comparing results across different manifests.
Unowned issues slipping through review cycles.
Waiving risks without expiry and validation plan.