SoC Integration · All levels

Interrupt Topology Contracts

Memory Maps & I/O: Interrupt architecture defines aggregation, priority, routing, and affinity policies that software relies on for deterministic response.

What this topic teaches

Interrupt Topology Contracts is about making top-level contracts measurable and enforceable. Interrupt architecture defines aggregation, priority, routing, and affinity policies that software relies on for deterministic response. The hard part is proving owner accountability and reproducibility under schedule pressure.

The senior-engineer question

When interrupt latency tail, missed-interrupt incidents moves, can you identify the first broken boundary, responsible owner, and smallest reversible fix with complete regression scope?

diagram
SOC INTEGRATION STACK — Interrupt Topology Contracts

program contract (scope, milestones, ownership)
        |
        v
architecture contract (budgets, interfaces, assumptions)
        |
        v
implementation contract (rtl, timing, physical, package)
        |
        v
validation contract (bring-up, workload, signoff evidence)
        |
        v
release contract (manifest, waivers, tapeout decision)

Debug rule: always identify which contract layer broke first.

Picture the integration flow

Start by drawing boundaries and ownership before diving into logs. The diagrams below are the whiteboard models to reproduce in reviews.

Interrupt topology

diagram
INTERRUPT TOPOLOGY

peripherals -> local aggregators -> global controller -> CPU targets
                       |
                priority + affinity policy

Integration sequence

diagram
SOC INTEGRATION FLOW — Interrupt Topology Contracts

requirements + budgets
        |
        v
IP handoff + collateral check
        |
        v
integration build + bring-up smoke
        |
        v
cross-domain signoff evidence
        |
        v
tapeout readiness decision

Metric in focus: interrupt latency tail, missed-interrupt incidents

Layer ownership

diagram
SOC INTEGRATION LAYERS — Interrupt Topology Contracts

layer               owns                          failure mode
-----------------   ---------------------------   ------------------------
architecture        partition + contracts         impossible budgets
ip handoff          models + collateral           integration mismatch
fabric/clock/reset  global behavior               domain deadlock
physical/package    route + SI/PI + IO            late closure churn
signoff process     manifests + waivers           non-reproducible claims
program governance  owners + escalations          schedule collapse

Evidence to collect

  • Primary metric: interrupt latency tail, missed-interrupt incidents.

  • Primary artifact: interrupt topology diagram, latency trace, affinity policy sheet.

  • Owners to include: firmware owner, platform architect, RTL owner.

  • Manifest baseline and revision for every claim.

  • One focused repro and one full-system regression result.

Ownership map

diagram
OWNERSHIP MAP — Interrupt Topology Contracts

artifact             owner
-----------------    -----------------
primary owner     firmware owner
co-owner          platform architect
review owner      RTL owner

No top-level issue should remain ownerless beyond one review cycle.

Subpages in this topic

Each topic includes 15 subpages: mechanism, inputs/outputs, reports, debug, worked example, pitfalls, interview, checklist, theory, design space, expanded case study, walkthrough, comparison matrix, software view, and silicon PPA impact.

Key takeaways

  • Tie every integration claim to a baseline manifest and owner.

  • Fix the first broken boundary before broad optimizations.

  • Regression scope is part of the fix, not a follow-up task.

Common pitfalls

  • Comparing results across changing baselines.

  • Unowned risks hidden behind green aggregate metrics.

  • Waiving high-impact issues without expiry and revalidation.

SoC deep dive

Address, interrupt, and IO contracts are where hardware/software alignment is won or lost.

Concept diagram

diagram
HW/SW CONTRACT
address map + interrupt model + io defaults -> firmware behavior

Metric graph

diagram
BOOT REGRESSION SOURCES
map churn █████
reset defaults ████
driver mismatch ███

Reports and artifacts

  • address decode audit

  • interrupt latency report

  • IO bring-up checklist

  • boot contract review

Mini case study

A map alias issue caused sporadic peripheral misconfiguration despite clean block-level tests.

Debug branches

  • Freeze address map baseline

  • Audit reset defaults

  • Validate firmware assumptions

Senior review question

Ask: what baseline, owner, and artifact prove this topic is truly closed?

Key takeaways

  • State baseline manifest and owner with every closure metric.

  • Run cross-domain regression after every top-level fix.

Common pitfalls

  • Comparing results across different manifests.

  • Unowned issues slipping through review cycles.

  • Waiving risks without expiry and validation plan.