Review checklist

Review Checklist for Interrupt Topology Contracts focuses on interrupt latency tail, missed-interrupt incidents. The goal is to map symptoms to boundary contracts, owner actions, and regression-proof closure.

• Baseline manifest and revision are explicit.

• Boundary contracts for this topic are current and approved.

• Ownership map covers all open issues.

• Focused and full regression evidence both exist.

• Residual risks are either closed or bounded via waiver policy.

• Owners signed: firmware owner, platform architect, RTL owner.

Signoff ownership

OWNERSHIP MAP — Interrupt Topology Contracts

artifact             owner
-----------------    -----------------
primary owner     firmware owner
co-owner          platform architect
review owner      RTL owner

No top-level issue should remain ownerless beyond one review cycle.

SoC deep dive

Address, interrupt, and IO contracts are where hardware/software alignment is won or lost.

Concept diagram

HW/SW CONTRACT
address map + interrupt model + io defaults -> firmware behavior

Metric graph

BOOT REGRESSION SOURCES
map churn █████
reset defaults ████
driver mismatch ███

Reports and artifacts

• address decode audit

• interrupt latency report

• IO bring-up checklist

• boot contract review

Mini case study

A map alias issue caused sporadic peripheral misconfiguration despite clean block-level tests.

Debug branches

• Freeze address map baseline

• Audit reset defaults

• Validate firmware assumptions

Senior review question

Ask: what baseline, owner, and artifact prove this topic is truly closed?

Key takeaways

• State baseline manifest and owner with every closure metric.

• Run cross-domain regression after every top-level fix.

Common pitfalls

• Comparing results across different manifests.

• Unowned issues slipping through review cycles.

• Waiving risks without expiry and validation plan.

Principal SoC review addendum

Interrupt architecture defines aggregation, priority, routing, and affinity policies that software relies on for deterministic response.

Metric: interrupt latency tail, missed-interrupt incidents