SoC Integration · All levels

Interrupt Topology Contracts: Comparison Matrix

Comparison Matrix for Interrupt Topology Contracts.

Comparison matrix

Address and interrupt policies trade flexibility with software stability.

diagram

+------------------+----------------+----------------+----------------+
| Approach         | Strength       | Weakness       | Best when      |
+------------------+----------------+----------------+----------------+
| Strict           | predictable    | slower early   | new program    |
| Balanced         | practical      | needs rigor    | stable teams   |
| Aggressive       | fast           | escape risk    | late schedule  |
| Re-architect     | durable        | expensive      | recurring failures |
+------------------+----------------+----------------+----------------+

When to choose each approach

Pick the approach based on residual silicon risk, not only schedule pressure.

Review traps

Policy-only arguments without artifact evidence
Unbounded waivers

Evidence comparison

diagram

INTEGRATION EVIDENCE MATRIX — Interrupt Topology Contracts

+-------------------+------------------------+--------------------------+-------------------------+
| Evidence           | Tells you              | Does not prove           | Next action             |
+-------------------+------------------------+--------------------------+-------------------------+
| Manifest diff      | baseline changed       | root cause itself        | isolate first delta     |
| Domain trace       | where behavior diverged| ownership accountability | map to contract owner   |
| Signoff dashboard  | closure posture        | reproducibility quality  | verify source artifacts |
| Bring-up logs       | software-visible symptom| physical/timing cause   | correlate with HW trace |
| Waiver register    | accepted residual risk | technical closure        | review expiry criteria  |
+-------------------+------------------------+--------------------------+-------------------------+

SoC deep dive

Address, interrupt, and IO contracts are where hardware/software alignment is won or lost.

Concept diagram

diagram

HW/SW CONTRACT
address map + interrupt model + io defaults -> firmware behavior

Metric graph

diagram

BOOT REGRESSION SOURCES
map churn █████
reset defaults ████
driver mismatch ███

Reports and artifacts

address decode audit
interrupt latency report
IO bring-up checklist
boot contract review

Mini case study

A map alias issue caused sporadic peripheral misconfiguration despite clean block-level tests.

Debug branches

Freeze address map baseline
Audit reset defaults
Validate firmware assumptions

Senior review question

Ask: what baseline, owner, and artifact prove this topic is truly closed?

Key takeaways

State baseline manifest and owner with every closure metric.
Run cross-domain regression after every top-level fix.

Common pitfalls

Comparing results across different manifests.
Unowned issues slipping through review cycles.
Waiving risks without expiry and validation plan.

Principal SoC review addendum

Interrupt architecture defines aggregation, priority, routing, and affinity policies that software relies on for deterministic response.

Metric: interrupt latency tail, missed-interrupt incidents

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