Front-end

The part of the chip flow that turns a spec into verified RTL and a checked netlist, before physical design begins.

Front-End and Back-End: Who Does What

Back-end

The part of the chip flow that turns a netlist into masks and silicon, covering placement, routing and sign-off checks.

Front-End and Back-End: Who Does What

RTL (register-transfer level)

A description of a design as registers and the logic between them, written in a hardware description language such as SystemVerilog.

What RTL Is

ASIC (application-specific integrated circuit)

A chip manufactured for one product, with high upfront cost and logic that cannot change after fabrication.

ASIC, FPGA, SoC and IP

FPGA (field-programmable gate array)

A chip whose logic you can reconfigure after manufacture, bought off the shelf and programmed for each application.

ASIC, FPGA, SoC and IP

SoC (system on chip)

One chip that holds processors, memories and peripherals that used to be separate parts.

ASIC, FPGA, SoC and IP

IP (intellectual property)

A reusable block, such as a counter or a bus interface, shared or bought instead of designed from scratch.

ASIC, FPGA, SoC and IP

EDA (electronic design automation)

The tools that compile, simulate, check and build chip designs, such as Icarus, Verilator and Yosys.

Installing and Checking Tools

PPA (performance, power, area)

The three costs traded against each other in every design decision: how fast, how much energy, how much silicon.

PPA Primer

Sign-off

The set of checks, including timing and physical verification, that must pass before a design is released for manufacture.

What Happens After RTL

Hand-off package

The bundle the front-end team delivers, with RTL, constraints, docs and version pins, so the back-end can build the chip.

The Release Package

Testable spec

A written behavior where every claim can be checked by a test, with numbers instead of vague words.

Writing a Testable Spec

Microarchitecture

The block diagram drawn from the spec, naming the registers and logic that will become RTL.

From Spec to Microarchitecture

Register contract

The agreed map of registers and fields that software and hardware both obey, checked by the golden model and the testbench.

Golden Model and Register Contract

Clock edge

The rising moment of the clock (posedge clk) when flops sample their inputs; this course samples on the rising edge.

First Simulation

Synchronous reset

A reset that takes effect on a clock edge, so it behaves like any other timed input.

Tests That Can Fail

Timescale

The directive (` timescale 1ns/1ps ``) that sets the time unit and precision of a file, so delays mean the same thing everywhere.

Compile, Elaborate, Simulate, Synthesize, Lint

Constraints

Timing and physical requirements, written in SDC (Synopsys Design Constraints) format, that tell the back-end tools what the design must meet.

Reading a Constraints File

DUT (device under test)

The design module the testbench drives and checks.

First Simulation

Testbench

The code around the DUT that drives inputs, checks outputs and reports whether the test passed.

Compile, Elaborate, Simulate, Synthesize, Lint

Simulation

Running the RTL and its testbench in software to see what the hardware would do, before anything is built.

First Simulation

Waveform

The drawing of signal values against time, read to find the cycle where behavior leaves intent.

Waveforms with GTKWave

VCD (value change dump)

The file format simulators write to record every signal change for a waveform viewer.

Waveforms with GTKWave

Mutant

A copy of the design with one deliberate bug, run to prove the testbench can fail.

Tests That Can Fail

Equivalent mutant

A mutant that still meets the spec, such as swapped reset and clear that both set the count to 0, which a good testbench keeps passing.

Tests That Can Fail

Golden model

A simple trusted program, often in Python, that computes the expected answers the RTL must match.

Self-Checking and Golden Model

Self-checking testbench

A testbench that compares the DUT against the golden model by itself and reports the result without you reading waves.

Self-Checking and Golden Model

Random stimulus

Test inputs drawn from a random generator instead of written by hand, so the test reaches cases you did not think of.

Random Stimulus and Seeds

Seed

The starting number of a random generator; the same seed repeats the same test, which makes failures reproducible.

Random Stimulus and Seeds

Assertion

A check written in the design or testbench that watches for a forbidden behavior every time it could happen.

Assertions

SVA (SystemVerilog Assertions)

The SystemVerilog language for writing assertions, with immediate checks at one point and concurrent properties over time.

Assertions

Coverage

The record of which behaviors the tests actually reached, used to find untested corners.

Coverage

Formal verification

Proving a property holds for all possible inputs with math, instead of trying inputs one by one in simulation.

Formal in One Lesson

Elaboration

The step where the tool builds the design hierarchy from the compiled files, resolving parameters and generates before simulation or synthesis.

Compile, Elaborate, Simulate, Synthesize, Lint

Lint

Static checks on RTL that flag likely bugs without running anything, such as widths that do not match.

Lint with Verilator

Synthesis

Turning RTL into a netlist of gates for a target library, the step that shows what the code really infers.

First Synthesis Check

Netlist

The list of gates and wires produced by synthesis, describing the same behavior as the RTL in hardware terms.

First Synthesis Check

Synthesizable code

RTL written in the subset that maps to hardware, as opposed to simulation-only code such as delays that synthesis ignores.

Simulation Code vs Synthesizable Code

Shell

The text prompt where you run commands; this course uses the same commands on macOS, Linux and WSL.

Shell Survival Kit

Git

The version control tool that saves snapshots of your work so you can compare versions and undo mistakes.

Git: Save, Compare, Undo

Icarus Verilog

The free simulator this course uses to compile with iverilog and run with vvp.

First Simulation

Verilator

The free tool this course uses to lint RTL and to run the assertion testbench.

Lint with Verilator

Yosys

The free synthesis tool this course uses for the first synthesis check.

First Synthesis Check

GTKWave

The free waveform viewer this course uses to read VCD files.

Waveforms with GTKWave

Makefile

The file that names each flow step as a target, so one command reruns the whole loop the same way every time.

Makefile for the Loop

Exit code

The number a command returns when it finishes: 0 means success and anything else means failure, which make and CI read to decide pass or fail.

Exit Codes and Pass Markers

Pass marker

A short line at the end of a tool log that shows the step passed, which the Makefile counts to confirm success.

Exit Codes and Pass Markers

CI (continuous integration)

A server that runs the smoke test on every change, so a broken commit is caught the same day.

CI Smoke Test

Smoke test

The short test that runs on every change to catch breakage fast.

CI Smoke Test

Regression

The longer suite that reruns many tests, often nightly, to catch bugs a change dragged in elsewhere.

Smoke vs Nightly