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Course contents

  • How to Use This Course
  • Reading Paths
  • Quick Start: Your First Green Build
  • Part 1: How Chips Get Made6
  • Part 2: Your Workstation5
  • Part 3: Specify and Architect3
  • Part 4: The Design Loop6
  • Part 5: The Verification Ladder6
  • Part 6: Automation and Reproducibility5
  • Part 7: Hand-Off to the Back-End3
  • Part 8: When Things Go Wrong3
  • Part 9: Project and Next Steps3
  • Reference4
    • Syntax Primer
    • Glossary
    • Command Cheat Sheet
    • Tool Versions
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‹Reference
  1. Topics
  2. Start Here: RTL and Verification
  3. Reference
  4. Tool Versions

Reference · Working (W)

Tool Versions

The tool versions the course examples were tested with, and how to check your own.

On this page

    The course examples were tested with the versions below. When a command fails on your machine, compare your versions against this table before anything else.

    Tested versions

    Measured on 2026-10-21: make check-tools && make all plus the Python model passed on both columns.

    Tool

    macOS (Homebrew)

    Ubuntu 24.04.5 aarch64 (apt)

    Icarus Verilog

    13.0

    12.0

    Verilator

    5.048

    5.020

    Yosys

    0.69+post

    0.33

    GNU Make

    3.81

    4.3

    Git

    2.54.0

    2.43.0

    Python

    3

    3

    Result

    make all passes

    make all passes

    Not yet tested

    • x86-64 Linux (the GitHub runner architecture).

    • Windows with WSL.

    • The CI workflow itself.

    • GTKWave version.

    Print your own versions

    Run this in the example project folder. It runs scripts/check_tools.sh, which prints one line per tool and exits 1 when a tool is missing.

    Diagram
    make check-tools

    How to compare

    • Match each printed line against the table row for your platform.

    • Small version differences are common; when a command fails, the version gap is the first suspect.

    • When your versions sit far from the table and make all fails, install the listed ones following Installing and Checking Tools, then rerun make check-tools.

    • Record the versions you used with Pinning Tool Versions, so a fresh machine reproduces your results.

    Documentation links

    • Icarus Verilog documentation

    • Verilator documentation

    • Yosys documentation

    • GNU Make manual

    • Git documentation

    • GitHub Actions documentation

    • GTKWave

    • IEEE 1800 (SystemVerilog)

    Related topics

    • Course hub

    • Glossary

    • Command cheat sheet

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    See also

    • Syntax Primer
    • Glossary