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Course contents

  • Start Here6
  • SystemVerilog Language Foundations28
  • Object-Oriented SystemVerilog for Verification30
  • Constraint Randomization — Interview-Critical Deep Dive36
  • SystemVerilog Assertions — Interview-Critical Deep Dive40
  • Functional Coverage in SystemVerilog22
  • Testbench Architecture in SystemVerilog23
  • Advanced Language & Integration25
  • Senior & Interview Preparation21
  • Principal-Level Verification28
    • Reusable Testbench Architecture
    • Checking Out-of-Order Traffic
    • Assertion Depth
      • Abort Operators
      • Recursive Properties
      • let and Property Libraries
      • Local Variables for IDs
      • Formal-Ready Assertions
    • Coverage Modelling for Real Features
    • Capstone: Out-of-Order Memory Controller
    • Principal Judgment
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‹Principal-Level Verification
  1. Topics
  2. SystemVerilog
  3. Principal-Level Verification
  4. Assertion Depth

Part 9 · Principal-Level Verification · Advanced

Assertion Depth

Abort operators, recursive properties, let and property libraries, local variables that match IDs, and assertions written for formal tools.

  • 5topics
  • 5lessons

Part 4 taught the SVA operators one by one. This topic covers what senior engineers are asked to own: properties that end early on purpose, properties that carry state through recursion, assertion libraries shared by many blocks, ID tracking under outstanding traffic, and assertions a formal tool can prove.

The free simulator here (Verilator 5.048 with --assert) runs only part of SVA. Each lesson tells you what ran, what did not, and how the meaning was checked instead: against the IEEE 1800 text, with a trace table, or with an equivalent check that does run.

Diagram
WHERE EACH LESSON SITS

  property ends early on an event ......... abort operators   (accept_on, reject_on, sync_*)
  property carries state cycle to cycle .... recursive properties
  one rule, many blocks .................... let + parameterized properties + bind
  one rule, many transactions in flight .... local variables (one copy per attempt)
  one rule, proved instead of simulated .... formal-ready assertions (assume, liveness)

Lesson

What it covers

Abort Operators

accept_on, reject_on and their sync forms, how they differ from disable iff, and an unrolled rewrite that runs here.

Recursive Properties

Properties that instantiate themselves, the four LRM restrictions, and when recursion beats repetition.

let and Property Libraries

let helpers, parameterized properties and one checker library bound to two different DUTs.

Local Variables for IDs

Matching responses to requests by ID under out-of-order traffic, and the table rules local variables cannot express.

Formal-Ready Assertions

assume and restrict, safety versus liveness, s_eventually, and habits that let a formal tool use your assertions.

What Verilator 5.048 ran in our tests

These results come from small directed tests run while writing this topic. Other tools and later versions differ, so treat the table as a map of this site's runnable examples, not as a statement about SVA.

Construct

Result with verilator --assert

accept_on, reject_on, sync_accept_on, sync_reject_on

Rejected: "Unsupported"

Recursive property

Rejected: "Unsupported: Recursive property call"

s_eventually, s_until, s_until_with, s_nexttime, s_always, nexttime, always, eventually[ ], strong( ), weak( )

Rejected: "Unsupported"

until, until_with, implies, assume, restrict, let, checker

Compiled; until gave correct results on our traces

##[m:n] b as the last element of a consequent

Correct on our traces

##[m:n] x ##1 y, x[->1] ##0 y

Wrong verdicts on our traces

s |=> b[*3] and s |-> b[*3]

Missed failures: when b held for the first repetition and dropped on the second, no failure was reported. The written-out b ##1 b ##1 b failed correctly on the same trace

Local variables in properties

Compiled, but the value was not held: the check used the signal's current value

Several attempts failing in the same cycle

Action block ran once, so counts are per cycle, not per attempt

Check yourself A property compiles in your simulator. Does that mean the simulator evaluates it correctly?

No. Several constructs in the table compile and still give wrong verdicts. Before trusting a new construct in a tool, run a short directed trace where you know the answer, including one that must fail.

Interview

Senior assertion questions rarely ask for syntax. They ask what a property means at the edge cases: an abort on the last cycle, an ID reused while outstanding, a liveness check that can never fail in simulation. Each lesson ends with one of those.

Related topics

  • Part 9 hub: Principal-Level Verification

  • Part 4: SystemVerilog Assertions

  • Advanced SVA: Local Variables, Multiclock and More

  • Previous topic: Checking Out-of-Order Traffic

  • Next topic: Coverage Modelling

PreviousNext: Abort Operators

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See also

  • Reusable Testbench Architecture
  • Checking Out-of-Order Traffic
  • Coverage Modelling for Real Features