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Course contents

  • Start Here6
  • SystemVerilog Language Foundations28
  • Object-Oriented SystemVerilog for Verification30
  • Constraint Randomization — Interview-Critical Deep Dive36
  • SystemVerilog Assertions — Interview-Critical Deep Dive40
  • Functional Coverage in SystemVerilog22
  • Testbench Architecture in SystemVerilog23
  • Advanced Language & Integration25
  • Senior & Interview Preparation21
  • Principal-Level Verification28
    • Reusable Testbench Architecture
      • Policy Classes
      • Abstract BFM
      • Parameterized Interfaces
      • Interface Classes
      • Layered Stimulus
    • Checking Out-of-Order Traffic
    • Assertion Depth
    • Coverage Modelling for Real Features
    • Capstone: Out-of-Order Memory Controller
    • Principal Judgment
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‹Principal-Level Verification
  1. Topics
  2. SystemVerilog
  3. Principal-Level Verification
  4. Reusable Testbench Architecture

Part 9 · Principal-Level Verification · Advanced

Reusable Testbench Architecture

Policy classes, abstract BFMs, parameterized interfaces, interface classes and layered stimulus: the SystemVerilog patterns that let one environment serve many tests and many configurations.

  • 5topics
  • 5lessons

A testbench is reusable when a new test, a new bus width or a new checker means adding a file, not editing five. This topic covers the five patterns that make that true. Each one removes a specific kind of coupling between the parts of an environment.

Every lesson has a runnable, self-checking bench and names the change that makes it fail. The capstone of this part builds its environment from the policy and abstract-BFM patterns shown here.

Diagram
WHAT EACH PATTERN DECOUPLES

  test ──────────► stimulus rules      policy classes        (rules are objects, not subclasses)
  env  ──────────► pin-level details   abstract BFM          (env holds a class handle, not a vif)
  env  ──────────► bus parameters      parameterized vifs    (widths live in one typedef)
  env  ──────────► checker classes     interface classes     (registry knows contracts only)
  test ──────────► protocol beats      layered stimulus      (scenario -> transaction -> beat)

Lesson

What it covers

Policy Classes

Constraints as reusable objects instead of a subclass per combination; runtime policy lists and compile-time policy layers.

Abstract BFM

An abstract class API with the concrete BFM inside the interface, so the environment never sees a virtual interface or a width.

Parameterized Interfaces

Why virtual bus_if #(W) spreads through an environment, and how typedefs, config objects and width guards contain it.

Interface Classes

Contracts with interface class and implements for plug-in checkers and callbacks, including multiple API inheritance.

Layered Stimulus

Scenario, transaction and beat layers joined by bounded mailboxes, with back-pressure flowing up and a monitor that rebuilds bursts.

Check yourself Your environment has a driver class written for a 32-bit bus. A new project uses the same protocol at 64 bits. Which two lessons in this topic address the change, and how do they differ?

Parameterized Interfaces keeps the vif but makes the width a parameter that every class touching the vif carries. Abstract BFM hides the vif behind an abstract class, so the environment carries no parameter at all. The first is simpler for one width change; the second scales when many widths or variants coexist.

Interview

Likely question: “How do you make a testbench reusable across projects?” A strong answer names the coupling each pattern removes, not just the pattern: tests should add rules without new subclasses, the environment should not know the pin widths, and checkers should plug in through a contract.

Related topics

  • Part 9 hub: Principal-Level Verification

  • The Layered Testbench (Part 7)

  • OOP Patterns for Testbenches

  • Next topic: Checking Out-of-Order Traffic

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See also

  • Checking Out-of-Order Traffic
  • Assertion Depth
  • Coverage Modelling for Real Features