This page is a revision map, not a second source. Each answer below is the ten-second version; the solver math and the sequence depth live in the drills topics.
If the interviewer asks | Revise in |
|---|---|
Even values, | |
Overlapping versus non-overlapping implication, vacuity, repetition, past values, reset handling | |
What coverage proves and when it closes |
Zero the low bits: addr[0] == 1'b0 for even, addr[1:0] == 2'b00 for multiples of four. The bit form shows hardware thinking; multiples of 2 to the N have N low zeros.
:= weights each value in the range; :/ shares one weight across the range. Both forms also define the legal set: unlisted values can never generate.
A soft constraint is a default the solver drops silently whenever any hard constraint contradicts it. Two contradicting soft constraints resolve by declaration order, derived over base.
Only the distribution, never the legal set. Solving the rare flag first equalizes branch probabilities that uniform pair-picking would skew.
A with block adds one-call hard constraints layered over the class constraints. Names resolve to the object first, so a local with the same name is shadowed; local:: reaches the test scope.
randc permutes through every legal value exactly once per cycle. It fits small fields only: no dist, solved before plain rand, and the cycle restarts when constraints change.
The one-liners below are fragments, so this course's checks do not run them.
// snippet
// rand bit [7:0] addr;
// constraint c_even { addr[0] == 1'b0; }
// constraint c_len { len dist { 1 := 50, [2:9] := 5 }; }
// constraint c_dflt { soft len inside {[1:8]}; }
// constraint c_ord { solve err before code; }
// assert(t.randomize() with { len == local::len; });
// randc bit [1:0] chan; // cycles 0,1,2,3 in a fresh orderThe bit math behind the even-value answer runs here directly. The testbench proves the low-bit mask matches modulo for all 256 byte values.
module tb_even_bits;
bit [7:0] vec;
int errors = 0;
initial begin
for (int v = 0; v < 256; v++) begin
vec = v[7:0];
if ((vec[0] == 1'b0) !== (v % 2 == 0)) errors++;
if ((vec[1:0] == 2'b00) !== (v % 4 == 0)) errors++;
end
if (errors == 0) $display("PASS: low-bit masks match modulo for all 256 byte values");
else $fatal(1, "FAIL: evenness check wrong");
$finish;
end
endmodule|-> is overlapping: the consequent starts the same cycle the antecedent completes. |=> waits one cycle; a |=> b equals a |-> ##1 b.
Registered responses need the non-overlapping form. Demanding a same-cycle answer from flopped logic fails correct RTL.
An implication passes vacuously whenever its antecedent never matches, checking nothing. The standing defense is a cover on every antecedent, audited at closure.
Consecutive [*N] needs N back-to-back cycles. Goto [->N] lands exactly on the Nth occurrence. Non-consecutive [=N] counts N occurrences but its endpoint floats, so chaining ##1 after it anchors to the wrong place.
Before N ticks of history exist, $past returns the type's default value (X for 4-state, 0 for 2-state), so gate the opening cycles. disable iff aborts in-flight attempts asynchronously; an antecedent guard only checks reset at attempt start.
Assertions sample in the Preponed region, like flops. Waveform cursors showing post-edge values explain most false alarms.
The one-liners below are fragments, so this course's checks do not run them. Placed in a module with the signals declared, they run under verilator --assert.
// snippet
// a_same: assert property (@(posedge clk) req |-> gnt);
// a_next: assert property (@(posedge clk) req |=> gnt);
// c_req: cover property (@(posedge clk) req);
// a_burst: assert property (@(posedge clk) start |-> (beat [->3]) ##1 done);
// a_stable: assert property (@(posedge clk) disable iff (!rst_n)
// (valid && !ready) ##1 valid |-> data == $past(data));The timing idea runs here as plain procedural checks. A combinational path answers same-cycle and a flopped path answers next-cycle, which is exactly how the two operators split.
module two_path_dut (
input logic clk,
input logic req,
output logic gnt_comb,
output logic gnt_reg
);
assign gnt_comb = req;
always_ff @(posedge clk) gnt_reg <= req;
endmodule
module tb_implication;
timeunit 1ns; timeprecision 1ps;
logic clk = 0;
always #5 clk = ~clk;
logic req, gnt_comb, gnt_reg;
two_path_dut dut (.*);
int errors = 0;
initial begin
req = 0; @(posedge clk); #1;
req = 1; #1;
if (gnt_comb !== 1'b1) errors++; // overlapping: same-cycle answer
@(posedge clk); #1;
if (gnt_reg !== 1'b1) errors++; // non-overlapping: next-cycle answer
req = 0;
@(posedge clk); #1;
if (gnt_reg !== 1'b0) errors++;
if (errors == 0) $display("PASS: combinational path answers same-cycle and flopped path next-cycle");
else $fatal(1, "FAIL: response timing wrong");
$finish;
end
endmoduleThree checkers divide the work: the scoreboard catches data and ordering bugs, assertions catch cycle-accurate protocol violations, and coverage proves what was exercised. Coverage catches nothing by itself.
A cover on every assertion antecedent turns vacuity from a silent hole into a coverage number. Zero-hit covers at closure name the behaviors no test ever reached.
The manual counter below is the runnable shape of a covergroup: bins, hits and a closure check. It proves all three request classes were exercised.
module tb_manual_cover;
timeunit 1ns; timeprecision 1ps;
logic [1:0] req;
int hit_idle = 0, hit_single = 0, hit_multi = 0;
int errors = 0;
initial begin
for (int r = 0; r < 4; r++) begin
req = r[1:0]; #1;
case (req)
2'b00: hit_idle++;
2'b01, 2'b10: hit_single++;
default: hit_multi++;
endcase
end
if (hit_idle !== 1 || hit_single !== 2 || hit_multi !== 1) errors++;
if (errors == 0) $display("PASS: manual bins saw idle once, single twice and multi once");
else $fatal(1, "FAIL: coverage count wrong");
$finish;
end
endmodulelen dist { 1 := 50, [2:9] := 5 }: what weight does each value from 2 to 9 carry, and can 10 generate?Each carries weight 5, and 10 can never generate. The dist defines the legal set as well as the weights.
Nothing. The passes are vacuous, which is why every assert ships with a cover on its antecedent.