Review checklist

Review Checklist for Boundary Cell Design focuses on boundary violation count, level-shifter coverage, clamp correctness. The goal is to connect observed symptom to boundary mechanism, ownership, and signoff risk.

• Boundary assumptions are versioned and signed.

• Mode matrix (power/clock/reset/stress) is explicit.

• Physical context (floorplan/package/power) is included where relevant.

• Metric and artifact references are reproducible.

• Waivers have owner, expiry, and mitigation.

• Owners signed: AMS integration lead, digital implementation owner, library owner.

Sign-off ownership

OWNERSHIP MAP — Boundary Cell Design

artifact                  owner
----------------------    -----------------------------
integration artifact    AMS integration lead
implementation artifact digital implementation owner
signoff artifact        library owner

Every boundary issue needs a named owner before fixes start.

AMS deep dive

Boundary assumptions must be explicit, versioned, and testable.

Concept diagram

BOUNDARY CONTRACT FLOW

analog intent -> boundary implementation -> digital wrapper -> signed review

Metric graph

BOUNDARY RISK MIX

missing boundary cells    ███████
stale handoff assumptions ██████
silent mode changes       ████

Reports and artifacts

• boundary-cell coverage

• isolation/ESD review

• handoff contract checklist

• integration waiver log

Mini case study

Noise bursts traced to missing isolation clamp on one low-power transition mode.

Debug branches

• Validate boundary-cell insertion

• Diff handoff assumptions

• Reproduce with tagged mode sequence

Senior review question

Ask: what boundary condition proves this topic is actually closed?

Key takeaways

• State boundary, mode, and evidence tag with every claim.

• Always align analog, digital, and physical owners before signoff decisions.

Common pitfalls

• Fixing averages while tails still fail.

• Skipping package/supply evidence in jitter or SerDes issues.

• Shipping with waivers that lack owner and expiration criteria.

Principal AMS review addendum

Boundary cells protect logic domains at analog interfaces by enforcing voltage tolerance, clamp behavior, and legal signal ownership during power sequencing.

Metric: boundary violation count, level-shifter coverage, clamp correctness